AlteraFPGA在线重配置实现笔记_alterafpga重新配置资源-CSDN文库

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Altera

EPCS4

FPGA重配置

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10_Altera FPGA在线重配置.zip （4个子文件）

10_Altera FPGA在线重配置

EPCS在线配置实现笔记_V00_00_01_KeyWord_EPCS_EPCS04_FPGA在线升级_FPGA程序更新_Altera FPGA升级.vsd 40KB

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Serial Configuration (EPCS) Devices Datasheet.pdf 1.09MB

基于对EPCS在线编程的FPGA可重构方法.pdf 890KB

January 2012 Altera Corporation

C51014-4.0 Datasheet

QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark

Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their

respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor

products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use

of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders

for products or services.

101 Innovation Drive

San Jose, CA 95134

www.altera.com

ISO

9001:2008

Registered

Serial Configuration (EPCS) Devices

Datasheet

This datasheet describes serial configuration (EPCS) devices.

Supported Devices

Ta bl e 1 lists the supported Altera



EPCS devices.

f For more information about programming EPCS devices using the Altera

Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera

Programming Hardware Datasheet.

f The EPCS device can be re-programmed in system with ByteBlaster



II download

cable or an external microprocessor using SRunner. For more information, refer to

AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.

Features

EPCS devices offer the following features:

■ Supports active serial (AS) x1 configuration scheme

■ Easy-to-use four-pin interface

■ Low cost, low pin count, and non-volatile memory

■ Low current during configuration and near-zero standby mode current

■ 2.7-V to 3.6-V operation

■ EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated

circuit (SOIC) package

■ EPCS64 and EPCS128 devices available in 16-pin SOIC package

Table 1. Altera EPCS Devices

Device

Memory Size

(bits)

On-Chip

Decompression

Support

ISP Support

Cascading

Support

Reprogrammable

Recommended

Operating

Voltage (V)

EPCS1 1,048,576 No Yes No Yes 3.3

EPCS4 4,194,304 No Yes No Yes 3.3

EPCS16 16,777,216 No Yes No Yes 3.3

EPCS64 67,108,864 No Yes No Yes 3.3

EPCS128 134,217,728 No Yes No Yes 3.3

Page 2 Functional Description

Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation

■ Enables the Nios



processor to access unused flash memory through AS memory

interface

■ Reprogrammable memory with more than 100,000 erase or program cycles

■ Write protection support for memory sectors using status register bits

■ In-system programming (ISP) support with SRunner software driver

■ ISP support with USB-Blaster



, EthernetBlaster, or ByteBlaster II download cables

■ Additional programming support with the APU and programming hardware

from BP Microsystems, System General, and other vendors

■ By default, the memory array is erased and the bits are set to

Functional Description

To configure a system using an SRAM-based device, each time you power on the

device, you must load the configuration data. The EPCS device is a flash memory

device that can store configuration data that you use for FPGA configuration purpose

after power on. You can use the EPCS device on all FPGA that support AS x1

configuration scheme.

For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the

EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from

the EPCS64 device to the EPCS128 device.

With the new data decompression feature supported, you can determine using which

EPCS device to store the configuration data for configuring your FPGA.

Example 1 shows how you can calculate the compression ratio to determine which

EPCS device is suitable for the FPGA.

f For more information about the FPGA decompression feature, refer to the

configuration chapter in the appropriate device handbook.

Example 1. Compression Ratio Calculation

EP4SGX530 = 189,000,000 bits

EPCS128 = 134,217,728 bits

Preliminary data indicates that compression typically reduces the

configuration bitstream size by 35% to 55%. Assume worst case that is 35%

decompression.

189,000,000 bits x 0.65 = 122,850,000 bits

The EPCS128 device is suitable.

Active Serial FPGA Configuration Page 3

Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation

Figure 1 shows the EPCS device block diagram.

Accessing Memory in EPCS Devices

You can access the unused memory locations of the EPCS device to store or retrieve

data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for

creating bus-based (especially microprocessor-based) systems in Altera devices.

SOPC Builder assembles library components such as processors and memories into

custom microprocessor systems.

SOPC Builder includes the EPCS device controller core, which is an interface core

designed specifically to work with the EPCS device. With this core, you can create a

system with a Nios embedded processor that allows software access to any memory

location within the EPCS device.

Active Serial FPGA Configuration

The following Altera FPGAs support the AS configuration scheme with EPCS devices:

■ Arria



series

■ Cyclone



series

■ All device families in the Stratix



series except the Stratix device family

There are four signals on the EPCS device that interface directly with the FPGA’s

control signals. The EPCS device signals are

DATA

DCLK

ASDI

, and

nCS

interface with

the

DATA0

DCLK

ASDO

, and

nCSO

control signals on the FPGA, respectively.

1 For more information about the EPCS device pin description, refer to Table 22 on

page 36.

Figure 1. EPCS Device Block Diagram

Control

Logic

I/O Shift

Memory

Array

Status RegisterAddress Counter

Decode Logic

Data Buffer

nCS

DCLK

DATA

ASDI

EPCS Device

Page 4 Active Serial FPGA Configuration

Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation

Figure 2 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using a download cable.

Figure 2. Altera FPGA Configuration in AS Mode Using a Download Cable

(1),

(4)

Notes to Figure 2:

(1) For more information about the V

value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

(1) V

(1)

10 kΩ 10 kΩ 10 kΩ

10 kΩ

(3)

Altera FPGA

EPCS Device (2)

Pin 1

N.C.

Active Serial FPGA Configuration Page 5

Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation

Figure 3 shows the configuration of an FPGA device in the AS configuration scheme

with an EPCS device using the APU or a third-party programmer.

In an AS configuration, the FPGA acts as the configuration master in the

configuration flow and provides the clock to the EPCS device. The FPGA enables the

EPCS device by pulling the

nCS

signal low using the

nCSO

signal as shown in Figure 2

and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device

using the

ASDO

signal. The EPCS device responds to the instructions by sending the

configuration data to the FPGA’s

DATA0

pin on the falling edge of

DCLK

. The data is

latched into the FPGA on the next

DCLK

signal’s falling edge.

1 Before the FPGA enters configuration mode, ensure that V

of the EPCS device is

ready. If V

is not ready, you must hold

nCONFIG

low until all power rails of EPCS

device are ready.

The FPGA controls the

nSTATUS

and

CONF_DONE

pins during configuration in the AS

mode. If the

CONF_DONE

signal does not go high at the end of configuration, or if the

signal goes high too early, the FPGA pulses its

nSTATUS

pin low to start a

reconfiguration. If the configuration is successful, the FPGA releases the

CONF_DONE

pin, allowing the external 10-k resistor to pull the

CONF_DONE

signal high. The FPGA

initialization begins after the

CONF_DONE

pin goes high. After the initialization, the

FPGA enters user mode.

f For more information about configuring the FPGAs in AS configuration mode or

other configuration modes, refer to the configuration chapter in the appropriate

device handbook.

Figure 3. Altera FPGA Configuration in AS Mode Using APU or a Third-party Programmer

(1),

(4)

Notes to Figure 3:

(1) For more information about the V

value, refer to the configuration chapter in the appropriate device handbook.

(2) EPCS devices cannot be cascaded.

(3) Connect the

MSEL[]

input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate

device handbook.

(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration

chapter in the appropriate device handbook.

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[]

nCEO

CONF_DONE

ASDO

(1) V

(1)

10 kΩ 10 kΩ 10 kΩ

(3)

Altera FPGA

EPCS Device (2)

N.C.

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zhaoyd422

2014-09-01

比较实用，参考一下
zhangchongan

2015-11-12

最近在看有关方面的东西，拿来参考一下
shirley_4

2015-11-12

首先吐槽下居然十分钟才能等到这次评论。。。然后资料内容大概是类似被动配置方式的通过cpu或cpld加载fpga，算不上部分重配置。也相当于是直接全配置，所谓的在线功能类似于直接通过jtag下载之类的。
lightman1234588

2022-04-27

不能使用？没有说明到底是将哪个文件写入EPCS中？
lta3015

2017-06-28

正在找这方面的资料，非常有用。。。赞赞赞。。。