Agilent34401A多用表_Agilent_34401A

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Pre-Production

This is a product in pre-production phase of development. Device Ramtron International Corporation

characterization is complete and Ramtron does not expect to change 1850 Ramtron Drive, Colorado Springs, CO 80921

the specifications. Ramtron will issue a Product Change Notice if (800) 545-FRAM, (719) 481-7000

any specification changes are made. www.ramtron.com

Rev. 2.4

Mar. 2008 Page 1 of 22

FM3204/16/64/256

Integrated Processor Companion with Memory

Features

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory

• Low Voltage Reset

• Watchdog Timer

• Early Power-Fail Warning/NMI

• Two 16-bit Event Counters

• Serial Number with Write-lock for Security

Processor Companion

• Active-low Reset Output for V

and Watchdog

• Programmable V

Reset Trip Point

• Manual Reset Filtered and Debounced

• Programmable Watchdog Timer

• Dual Battery-backed Event Counter Tracks

System Intrusions or other Events

• Comparator for Early Power-Fail Interrupt

• 64-bit Programmable Serial Number with Lock

Ferroelectric Nonvolatile RAM

• 4Kb, 16Kb, 64Kb, and 256Kb versions

• Unlimited Read/Write Endurance

• 10 year Data Retention

• NoDelay™ Writes

Fast Two-wire Serial Interface

• Up to 1 MHz Maximum Bus Frequency

• Supports Legacy Timing for 100 kHz & 400 kHz

• Device Select Pins for up to 4 Memory Devices

• Companion Controlled via 2-wire Interface

Easy to Use Configurations

• Operates from 2.7 to 5.5V

• Small Footprint 14-pin “Green” SOIC (-G)

• Pin Compatible with FM31xx Series

• Low Operating Current

• -40°C to +85°C Operation

Description

The FM32xx is a family of integrated devices that

includes the most commonly needed functions for

processor-based systems. Major features include

nonvolatile memory available in various sizes, low-

reset, watchdog timer, nonvolatile event counter,

lockable 64-bit serial number area, and general

purpose comparator that can be used for an early

power-fail (NMI) interrupt or other purpose. The

family operates from 2.7 to 5.5V.

The FM32xx family is software and pinout

compatible with the FM31xx family which also

includes a real-time clock. The common features

allow a system design that easily can be assembled

with or without timekeeping by simply selecting the

FM31xx or FM32xx, respectively.

Each FM32xx provides nonvolatile RAM available in

sizes including 4Kb, 16Kb, 64Kb, and 256Kb

versions. Fast write speed and unlimited endurance

allow the memory to serve as extra RAM or

conventional nonvolatile storage. This memory is

truly nonvolatile rather than battery backed.

The processor companion includes commonly needed

CPU support functions. Supervisory functions

include a reset output signal controlled by either a

low V

condition or a watchdog timeout. /RST goes

active when V

drops below a programmable

threshold and remains active for 100 ms after V

rises above the trip point. A programmable watchdog

timer runs from 100 ms to 3 seconds. The watchdog

timer is optional, but if enabled it will assert the reset

signal for 100 ms if not restarted by the host before

the timeout. A flag-bit indicates the source of the

reset.

A general-purpose comparator compares an external

input pin to the onboard 1.2V reference. This is

useful for generating an early warning power-fail

interrupt (NMI) but can be used for any purpose. The

family also includes a programmable 64-bit serial

number that can be locked making it unalterable.

Additionally the FM32xx offers a dual event counter

that tracks the number of rising or falling edges

detected on dedicated input pins. The counter can

optionally be battery backed and even battery

operated by attaching a backup power source to the

VBAK pin. If VBAK is connected to a battery or

capacitor, then events will be counted even in the

absence of V

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FM3204/16/64/256

Rev. 2.4

Mar. 2008 Page 3 of 22

Figure 1. Block Diagram

Pin Descriptions

Pin Name Type Pin Description

A0, A1 Input Device select inputs are used to address multiple memories on a serial bus. To select

the device the address value on the two pins must match the corresponding bits

contained in the device address. The device select pins are pulled down internally.

CNT1, CNT2 Input Event Counter Inputs: These battery-backed inputs increment counters when an edge is

detected on the corresponding CNT pin. The polarity is programmable. These pins

should not be left floating. Tie to ground if pins are not used.

PFO Output Power Fail Output: This is the early power-fail output.

/RST I/O Active low reset output with weak pull-up. Also input for manual reset.

SDA I/O Serial Data & Address: This is a bi-directional line for the two-wire interface. It is

open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.

The input buffer incorporates a Schmitt trigger for noise immunity and the output

driver includes slope control for falling edges. A pull-up resistor is required.

SCL Input Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the

part on the falling edge, and in on the rising edge. The SCL input also incorporates a

Schmitt trigger input for noise immunity.

PFI Input Early Power-fail Input: Typically connected to an unregulated power supply to detect

an early power failure. This pin should not be left floating.

VBAK Supply Backup supply voltage: A 3V battery or a large value capacitor. If V

<3.6V and no

backup supply is used, this pin should be tied to V

. If V

>3.6V and no backup

supply is used, this pin should be left floating and the VBC bit should be set.

VDD Supply Supply Voltage.

VSS Supply Ground

FRAM

Array

2-Wire

Interface

SCL

SDA

RST

A1, A0

PFO

PFI

VDD

VBAK

2.5V

Event

Counters

CNT1

CNT2

Special

Function

Registers

S/N

LockOu

1.2V

Watchdog

LV Detect

Switched Powe

Battery Backed

Nonvolatile

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FM3204/16/64/256

Rev. 2.4

Mar. 2008 Page 4 of 22

Overview

The FM32xx family combines a serial nonvolatile

RAM with a processor companion. The companion is

a highly integrated peripheral including a processor

supervisor, a comparator used for early power-fail

warning, nonvolatile event counters, and a 64-bit

serial number. The FM32xx integrates these

complementary but distinct functions that share a

common interface in a single package. Although

monolithic, the product is organized as two logical

devices, the FRAM memory and the companion.

From the system perspective they appear to be two

separate devices with unique IDs on the serial bus.

The FM32xx provides the same functions as the

FM31xx with the exception of the real-time clock.

This makes it easy to develop a common design that

can either include timekeeping by using the FM31xx

or exclude it by using the FM32xx. All other features

are identical. The register address map is even

preserved so that software can be identical.

The memory is organized as a stand-alone 2-wire

nonvolatile memory with a standard device ID value.

The companion functions are accessed under their

own 2-wire device ID. This allows the companion

functions to be read while maintaining the most

recently used memory address. The companion

functions are controlled by 16 special function

registers. The event counter circuits and related

registers are maintained by the power source on the

VBAK pin, allowing them to operate from battery or

backup capacitor power when V

drops below a set

threshold. Each functional block is described below.

Memory Operation

The FM32xx is a family of products available in

different memory sizes including 4Kb, 16Kb, 64Kb,

and 256Kb. The family is software compatible, all

versions use consistent two-byte addressing for the

memory device. This makes the lowest density

device different from its stand-alone memory

counterparts but makes them compatible within the

entire family.

Memory is organized in bytes, for example the 4Kb

memory is 512 x 8 and the 256Kb memory is 32,768

x 8. The memory is based on FRAM technology.

Therefore it can be treated as RAM and is read or

written at the speed of the two-wire bus with no

delays for write operations. It also offers effectively

unlimited write endurance unlike other nonvolatile

memory technologies. The 2-wire interface protocol

is described further on page 13.

The memory array can be write-protected by

software. Two bits in the processor companion area

(WP0, WP1 in register 0Bh) control the protection

setting as shown in the following table. Based on the

setting, the protected addresses cannot be written and

the 2-wire interface will not acknowledge any data to

protected addresses. The special function registers

containing these bits are described in detail below.

Write protect addresses WP1 WP0

None 0 0

Bottom 1/4 0 1

Bottom 1/2 1 0

Full array 1 1

Processor Companion

In addition to nonvolatile RAM, the FM32xx family

incorporates a highly integrated processor

companion. It includes a low voltage reset, a

programmable watchdog timer, battery-backed event

counters, a comparator for early power-fail detection

or other purposes, and a 64-bit serial number.

Processor Supervisor

Supervisors provide a host processor two basic

functions: detection of power supply fault conditions

and a watchdog timer to escape a software lockup

condition. All FM32xx devices have a reset pin

(/RST) to drive the processor reset input during

power faults (and power-up) and software lockups. It

is an open drain output with a weak internal pull-up

to V

. This allows other reset sources to be wire-

OR’d to the /RST pin. When V

is above the

programmed trip point, /RST output is pulled weakly

to V

. If V

drops below the reset trip point

voltage level (V

) the /RST pin will be driven low. It

will remain low until V

falls too low for circuit

operation which is the V

RST

level. When V

rises

again above V

, /RST will continue to drive low for

at least 100 ms (t

RPU

) to ensure a robust system reset

at a reliable V

level. After t

RPU

has been met, the

/RST pin will return to the weak high state. While

/RST is asserted, serial bus activity is locked out even

if a transaction occurred as V

dropped below V

A memory operation started while V

is above V

will be completed internally.

Figure 2 below illustrates the reset operation in

response to the V

voltage.

Figure 2. Low Voltage Reset

VDD

VTP

RPU

RST

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FM3204/16/64/256

Rev. 2.4

Mar. 2008 Page 5 of 22

The bits VTP1 and VTP0 control the trip point of the

low voltage detect circuit. They are located in register

0Bh, bits 1 and 0.

VTP1 VTP0

2.6V 0 0

2.9V 0 1

3.9V 1 0

4.4V 1 1

The watchdog timer can also be used to assert the

reset signal (/RST). The watchdog is a free running

programmable timer. The period can be software

programmed from 100 ms to 3 seconds in 100 ms

increments via a 5-bit nonvolatile register. All

programmed settings are minimum values and vary

with temperature according to the operating

specifications. The watchdog has two additional

controls associated with its operation, a watchdog

enable bit (WDE) and timer restart bits (WR). Both

the enable bit must be set and the watchdog must

timeout in order to drive /RST active. If a reset event

occurs, the timer will automatically restart on the

rising edge of the reset pulse. If not enabled, the

watchdog timer runs but has no effect on /RST. Note

that setting the maximum timeout setting (11111b)

disables the counter to save power. The second

control is a nibble that restarts the timer preventing a

reset. The timer should be restarted after changing the

timeout value.

The watchdog timeout value is located in register

0Ah, bits 4-0, and the watchdog enable is bit 7. The

watchdog is restarted by writing the pattern 1010b to

the lower nibble of register 09h. Writing this pattern

will also cause the timer to load new timeout values.

Writing other patterns to this address will not affect

its operation. Note the watchdog timer is free-

running. Prior to enabling it, users should restart the

timer as described above. This assures that the full

timeout period will be set immediately after enabling.

The watchdog is disabled when V

is below V

The following table summarizes the watchdog bits. A

block diagram follows.

Watchdog timeout WDT4-0 0Ah, bits 4-0

Watchdog enable WDE 0Ah, bit 7

Watchdog restart WR3-0 09h, bits 3-0

Figure 3. Watchdog Timer

Manual Reset

The /RST pin is bi-directional and allows the

FM32xx to filter and de-bounce a manual reset

switch. The /RST input detects an external low

condition and responds by driving the /RST signal

low for 100 ms.

Figure 4. Manual Reset

Note that an internal weak pull-up on /RST

eliminates the need for additional external

components.

Reset Flags

In case of a reset condition, a flag will be set to

indicate the source of the reset. A low V

reset or

manual reset is indicated by the POR flag, register

09h bit 6. A watchdog reset is indicated by the WTR

flag, register 09h bit 7. Note that the flags are

internally set in response to reset sources, but they

must be cleared by the user. When the register is

read, it is possible that both flags are set if both have

occurred since the user last cleared them.

Early Power Fail Comparator

An early power fail warning can be provided to the

processor well before V

drops out of spec. The

comparator is used to create a power fail interrupt

(NMI). This can be accomplished by connecting the

PFI pin to the unregulated power supply via a resistor

divider. An application circuit is shown below.

Figure 5. Comparator as Early Power-Fail Warning

1.2V ref

Regulator

VDD

FM32xx

To MCU

NMI input

CAL/PFO

PFI

Timebase

Counter

Watchdog

timeout

100 ms

clock

WDE

/RST

WR3-0 = 1010b to restart

FM32xx

Reset

Switch

RST

MCU

Switch

Behavior

RST

FM32xx

drives

100 ms

剩余21页未读，继续阅读

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