VMIC PCI 5565 底层编程手册

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VMIC 5565实时网卡底层编程手册。
COPYRIGHT AND TRADEMARKS The information in this document has been carefully checked and is believed to be entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the preparation of this manual, gE Fanuc Embedded Systems assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contained herein GE Fanuc Embedded Systems reserves the right to make any changes, without notice, to this or any of GE Fanuc Embedded Systems' products to improve reliability, performance, function, or design GE Fanuc Embedded Systems does not assume any liability arising out of the application or use of any product or circuit described herein; nor does GE Fanuc Embedded Systems convey any license under its patent rights or the rights of others For warranty and repair policies, refer to GE Fanuc Embedded Systems' Standard Conditions of Sale AMXbus, BITMODULE, COSMODULE, DMAbus, lOMax, loWorks Access, lOWorks Foundation, lOWorks Manager lOWorks Server, MAGICWARE, MEGAMODULE, PLC ACCELERATOR (ACCELERATION), Quick Link, RTnet, Soft Logic Link. SRTbus, TESTCAL. The Next Generation PLc, The Plc Connection TURBOMODULE UCLIO, UIOD. UPLC Visual Soft Logic Control(ler), VMEbus Access, VMEmanager, VMEmonitor, VMEnet, VMEnet II, VMEprobe and VMIC Shutdown are trademarks and The l/O Experts, The lO Systems Experts, The Soft Logic Experts, and The Total Solutions Provider are service marks of ge fanuc embedded Systems lOWorks, visual lOWorks and the vMic logo are registered trademarks of GE Fanuc Embedded Systems. Other registered trademarks are the property of their respective owners Copyright o 2007 by GE Fanuc Embedded Systems. All Rights Reserved This document shall not be duplicated nor its contents used for any purpose, unless granted express written permission from GE Fanuc Embedded Systems RoHS Compliance The RoHS product is free of lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBBs)and polybrominated diphenyl ethers(PBDEs). In conjunction with the WEEE (Waste Electrical Electronic Equipment) Directive 2002 /96/EC ( January 27, 2003) This page is intentionally left blank Table of contents List of Figures List of tables Overview Features PCI Local Bus compliance Vendor and device dentification 14 Subsystem vendor id and subsystem ID Comparison of the PCl-5565PIORC and the Classic VMIPCI-5565 Reference material list Physical description and specifications Safety Summary 着4 Ground the system Do Not Operate in an Explosive Atmosphere Keep Away from Live Circuits 19 Do Not Service or Adjust Alone Do Not Substitute Parts or Modify System Dangerous procedure warnings 19 Safety Symbols Used in This Manual Chapter 1- Theory of operation 21 Basic Operation Front Bezel lEd Indicators PCI-5565PIORC Register Sets Reflective Memory RAM Interrupt Circuits 23452g Network Interrupts Redundant transfer Mode of operation PC/-5565P/ORC Product Manual Rogue Packet Removal Operation Chapter 2-Configuration and Installation Unpacking Procedures Switch S1 and S2 Configuration Before Installation Switch S1 and S2 Configuration Physical Installation 23353 Front Panel description Cable Configuration 37 Connector Specification(Single and Multimode) PCI-5565PIORC Connectivity Chapter 3-Programming 334 PCI Configuration Registers Local Configuration Registers RFM Control and status Registers Board revision Register 955 Board id Register Node ID Register Local Control and Status Register 1 5566 Local Control and Status Register 1 Bit Definitions Local Interrupt Control Registers(LISR and LIER) Local Interrupt Status Register Local Interrupt Control Register Bit Definitions Local Interrupt Enable Register Network Target Data Register(NTD) Network Target Node Register(NTN) Network Interrupt Command Register(NIC) Interrupt 1 Sender Data FIFO Interrupt 1 Sender ID FIFO Interrupt 2 Sender Data FIFO Interrupt 2 Sender ID FIFO 4 Interrupt 3 Sender Data FIFO Interrupt 3 Sender ID FIFO 64 Interrupt 4 Sender Data FIFo nterrupt 4 Sender ID FIFO EXample of a DMA Operation for the PCl-5565PIORC Example of Network Interrupt Handling Setup Servicing Network Interrupts 68 6 Table of contents Maintenance Maintenance prints Compliance Information 71 CE International Compliance 72 European Union United states Australia/New Zealand pal 72 Canada FCC Part 15 73 FCC Class a Canadian Regulations PC/-5565P/ORC Product Manual This page is intentionally left blank List of Figures Figure PCI-5565PIORC Block Diagram 16 igure 2 Typical Reflective Memory Network Figure 1-1 PCl-5565PIORC Interrupt Circuitry block Diagram 27 Figure 2-1 PC1-5565PIORC Location of Switch S1 and S2 34 Figure 2-2 Installing the Pcl-5565PlORC 35 Figure 2-3 PC1-5565PIORC Front Panel 36 Figure 2-4 " LC Type Fiber-Optic Cable Connector 37 Figure 2-5 EXample: Six Node ring connectivity Figure 3-1 Block Diagram of the Network Interrupt Reception Circuitry PC//ORC Product Manual This page is intentionally left blank

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