ARMv7-M Architecture Reference Manual

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ARMv7-M Architecture Reference Manual Cortex-M seraials Instruction set
Note The term ARM is also used to refer to versions of the ARM architecture, for example arMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way Web address ARM DDI 0403E b Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved D120114 Non-Confidential Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved ARM DDI 0403E b Non-Confidential D120114 Contents ARMV7-M Architecture Reference Manual Preface about this manual X Using this manual..… Conventions X Further reading Feedback Part a Application Level Architecture Chapter A1 Introduction A1.1 About the ARMv7 architecture, and architecture profiles A1-20 A1.2 The ARMv7-M architecture profile A12 Al.3 Architecture extensions A122 Chapter a2 Application Level Programmers'Model A2. 1 About the application level programmers model A2-24 A2.2 ARM processor data types and arithmetic A225 A2.3 Registers and execution state A230 A2.4 EXceptions, faults and interrupts A233 A2.5 The optional floating-point extension A234 A2.6 Coprocessor support A261 Chapter A3 ARM Architecture Memory Model A3.1 Address space… A3-64 A3.2 Alignment support ∴A3-65 A3.3 Endian support A3-67 A3.4 Synchronization and semaphores A3-70 A3. 5 Memory types and attributes and the memory order model A3-78 ARM DDI 0403E b Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved D120114 Non-Confidential Contents A3.6 Access rights A3-87 A3.7 Memory access order A3-89 A3.8 Caches and memory hierarchy A3-96 Chapter A4 The army7-m instruction set A4.1 About the instruction set A4-100 A4 2 Unified Assembler Language A4-102 A4.3 Branch instructions A4-104 A4. 4 Data-processing instructions A4-105 A4.5 Status register access instructions A4-112 A4.6 Load and store instructions A4-113 A4.7 Load Multiple and Store Multiple instructions A4-115 A4 Miscellaneous instructions A4-116 A4.9 EXception-generating instructions A4-117 A4.10 Coprocessor instructions “ A4-118 A4.11 Floating-point load and store instructions A4-119 A4.12 Floating-point register transfer instructions A4-120 A4.13 Floating-point data-processing instructions A4-121 Chapter A5 The Thumb Instruction Set Encoding A5.1 Thumb instruction set encoding ..A5-124 A5.2 16-bit Thumb instruction encoding A5-127 A5.3 32-bit Thumb instruction encoding A5-135 Chapter A6 The Floating-Point Instruction Set Encoding A6.1 Overview A6-158 A6.2 Floating-point instruction syntax ∴A6-159 A6. 3 Register encoding A6-162 A6.4 Floating-point data-processing instructions A6-163 A6.5 EXtension register load or store instructions A6-165 A66 32-bit transfer between ARm core and extension registers .A6-166 A6.7 64-bit transfers between ARM core and extension registers A6-167 Chapter A7 Instruction Details A7.1 Format of instruction descriptions A7-170 A7.2 Standard assembler syntax fields A7-175 A7.3 Conditional eⅹ ecution∴ A7. 4 Shifts applied to a register A7-176 着着 A7-180 A7. 5 Memory accesses A7-182 A7, 6 Hint Instructions .:..4. A7-183 A7.7 Alphabetical list of ARMv7-M Thumb instructions A7-184 Part B System Level Architecture Chapter B1 System Level Programmers'Model B1. 1 Introduction to the system level B1-566 B1.2 About the ARMv7-M memory mapped architecture B1567 B1.3 Overview of system level terminology and operation B1-568 B1.4 Registers B1-572 B1.5 ARMv7-M exception model B1579 B1.6 Floating-point support ... B1-620 Chapter b2 System Memory Model B2.1 About the system memory model B2-626 B2.2 Caches and branch predictors B2-627 B2.3 Pseudocode details of general memory system operations B2638 Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved ARM DDI 0403E b Non-Confidential D120114 Contents Chapter B3 System Address Map B3. 1 The system address map B3-648 B3.2 System Control Space(SCs) B34 Nested Vectored Interrupt Controller,NVC.…,…… B3-651 B3.3 The system timer, Sys Tick...... .B3-676 B3-680 B3.5 Protected Memory System Architecture, PMSAV7 B3-688 Chapter b4 The CPUid Scheme B4.1 About the cpuid scheme B4-702 B4.2 Processor Feature ID Registers B4-704 B4.3 Debug Feature ID register B4-706 B4.4 Auxiliary feature id register 34-707 B4.5 Memory Model Feature Registers B4-708 B4.6 Instruction Set Attribute registers .B4-711 B4.7 Floating-point feature identification registers B4-720 B4.8 Cache Control Identification Registers B4-723 Chapter B5 System Instruction Details B5. 1 About the aRMv7-M system instructions .B5-728 B5.2 ARMv7-M system instruction descriptions B5-730 Part c Debug Architecture Chapter c1 ARMV7-M Debug C11 Introduction to ARMv7-M debug C1740 C1.2 The Debug Access Port C1-744 C1.3 ARMV7-M debug features C1746 Debug and reset C1-751 C1.5 Debug event behavior C1-752 C1.6 Debug system registers…… C1758 C1.7 The Instrumentation trace macrocell C1-769 C1. 8 The Data Watchpoint and trace unit C1-779 C1. 9 Embedded Trace Macrocell support C1809 C1.10 Trace Port Interface Unit C1810 C1. 11 Flash Patch and Breakpoint unit C1-815 Part d Appendixes Appendix d1 ARMV7-M Core Sight Infrastructure IDs D1. 1 Core Sight infrastructure IDs for an ARMv7-M implementation D1826 Appendix D2 Legacy Instruction Mnemonics D2. 1 Thumb instruction mnemonics D2-830 D2.2 Pre-UAL pseudo-instruction NOP D2-833 D2.3 Pre-UAL floating-point instruction mnemonics D2-834 Appendix D3 Deprecated Features in ARMv7-M D3. 1 Deprecated features of the ARMv7-M architecture .D3-838 Appendix D4 Debug ITM and DWT Packet Protocol D4.1 About the ITM and dWT packets.... D4-840 D4.2 Packet descriptions D4-842 D4.3 DWT use of Hardware source packets D4-850 ARM DDI 0403E b Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved D120114 Non-Confidential Contents AppendiX D5 ARMV7-R Differences D5.1 About the ARMv7-M and ARMv7-R architecture profiles D5858 D52 Endian support .D5-859 D5 3 Application level support..... D5-860 D5.4 System level support D5-86 D5.5 Debug support.. D5-862 Appendix d6 Pseudocode definition D6. 1 Instruction encoding diagrams and pseudocode D6-864 D6.2 Limitations of pseudocode .D6-866 D6 3 Data types D6-867 D6. 4 EXpressions D6-871 D65 Operators and built-in functions D6-873 D6.6 Statements and program structure D6-878 D6. 7 Miscellaneous helper procedures and functions .D6-882 Appendix D7 Pseudocode index D7. 1 Pseudocode operators and keywords D7-888 D7.2 Pseudocode functions and procedures…… .D7-891 Appendix D8 Register Index D8. 1 ARM core registers D8900 D8.2 Floating-point extension registers D8901 D83 Memory mapped system registers………… D8902 D8.4 Memory-mapped debug registers D8-905 Glossary Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved ARM DDI 0403E b Non-Confidential D120114 Preface This preface describes the contents of this manual, then lists the conventions and terminology it uses About this manual on page x Using this manual on pa age xI Convention.s on page xiii Further reading on pagc xiy Feedback on page xv ARM DDI 0403E b Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved D120114 Non-Confidential Preface About this manual About this manual This manual documents the microcontroller profile of version 7 of the ARM Architecture, the ARMv7-M architecture profile For short definitions of all the ARMv 7 profiles see About the ARMv7 architecture, and architecture profiles on page Al-20 The manual has the following parts Part A The application level programming model and memory model information along with the instruction set as visible to the application programmer This is the information required to program applications or to develop the toolchain components (compiler, linker, assembler and disassembler) excluding the dcbuggcr. For ARMv7-M, this is almost entirely a subset of material common to the other two profiles. Instruction set details that differ between profiles are clearly stated All ARMv7 profiles support a common procedure calling standard, the ARM Architecture Procedure Calling Standard(AAPCs) Part B The system level programming model and system level support instructions required for system configuration and control of processor resources and management of memory access rights es for correctness. The system level supports the ARMv7-M exception model. It also provides featu This is the information in addition to Part A required for an operating system(OS)and/or system support software. It includes details of register banking, the exception model, memory protection (management of access rights and cache support Part B is profile specific ARMv7-M introduces a new programmers model and as such has some fundamental differences at the system level from the other profiles. As ARMv7-M is a memory-mapped architecture, the system memory map is documented here Part c The debug features to support the aRMv7-M debug architecture and the programming interface to the debug environment This is the information required in addition to Parts a and b to write a debugger Part C covers details of the different types of debug Halting debug and the related debug state Exception-based monitor debug Non- invasivc support for event generation and signalling of the events to an cxtcrnal agent This part is profile specific and includes several debug features that are supported only in the ARMv7-M architecture profile Appendices The appendices give information that relates to, but is not part of, the ARMv7-M architecture profile specification X Copyright O 2006-2008, 2010, 2014 ARM. All rights reserved ARM DDI 0403E b Non-Confidential D120114

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