Altera External Memory Interface Handbook

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Altera External Memory Interface Handbook
AAUERA External Memory Interface Handbook volume 1 Section about this handbook A吉RA 101 Innovation Drive San jose. ca 95134 www.altera.com EMI INTRO ABOUT-2 Document last updated for Altera Complete Design Suite version 10.1 Document publication date: December 2010 Subscribe (2010 Altera Corporation All rights reserved. ALTERA, ARKLA, CYCLONE, HARDCOPY, MAX, MEGACORE, MIOS, QUARIUS and StRAllX are Reg. L.S.Pat. &r'Im. Off. and/or trademarks of Alte rporation in the U.Sane countries. All o:her trademarks and service marks are the property of their holdersasdescribedatwww.altera.com/common/legal.html.Alterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsina with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or ability arising out of pplication or use of any information, product, or service described herein except as expressly agreed to ir writing by Altera.Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or NSA Certified External Memory Interface Handbook Volume 1 December 2010 Altera Corporation Section L. about this handbook AERA Contents Chapter 1. How to Use this Handbook Introduction to Altera External memory Interfaces Device, Pin, and Board Layout Guidelines Implementing Altera Memory Interface IPs Simulation, Timing Analysis, and Debugging Implementing a Custom PHY Design Flow Tutorials Chapter 2. Recommended Design Flow Sclect a device,……… Determine board layout Perform Board-Level Simulations 2-3 Device-Side Termination Memory-Side termination Adjust Termination and Drive Strength Instantiate PhY and Controller 2-4 Verify Timing Adjust Constraints Perform Timing simulation Verify design Functionality Design Checklis Chapter 3. Glossary December 2010 Altera corporation External Memory Interface Hand book Volume 1 Section l, about this handbook External Memory Interface Handbook Volume 1 December 2010 Altera Corporation Section L, about this handbook ZAERA 1. How to Use this handbook The External memory Interface Handbook contains information that you require to implement an external memory interface. The handbook focuses on the altera olution for DDR, DDR2, DDR3 SDRAM; QDR II and QDR II SRAM; and RLDRAM II interfaces. The handbook is organized with a typical design flow in mind, into the following six volumes a" Introduction to Altera External Memory Interfaces Device, pin, and board layout guidelines Implementing Altera Memory Interface IPs Simulation, Timing Analysis, and Debugging Implementing a Custom PHY Design Flow Tutorials ntroduction to Altera External Memory Interfaces This volume includes this How to llse this Handbook chapter, recommended desigr flow, and a glossary In addition this volume includes basic information for various memory standards Verifications section lists a complete scorecard of Altera device family support for various memory standards Device. Pin, and board layout guidelines This volume describes the initial steps of selecting the correct Altera device with the right resources and number of user i/o available for that interface The second section of the volume describes how you can select the correct termination and drive strength based on your board simulation for ddR, ddr2, and ddr3 SDRAM interfaces. it offers board results correlated with board simulation and the Altera recommended settings based on this correlation Implementing Altera Memory Interface IPs This volume covers the following Altera memory Ip products DDR and DDR2 SDRAM High Performance Controllers DDR and DDR2 SDRAM High Performance Controllers II ddR3 SDRAM High performance Controllers QDR II and qdr I+ sram controllers with UniphY RI DRAM TI Controllers with UniPhY December 2010 Altera corporation External Memory Interface Hand book Volume 1 Section l, about this handbook Chapter 1: How to Use this Handbook Simulation, Timing Analysis, and Debugging Each iP has two modules: the phy and the memory controller. The ddr, ddr2, and DDR3 SDRAM high-performance controllers use the Altera ALTMEMPHY megafunction for the PhY, which you can use standalone from the controller. The QDR IL, QDR II+, and RLDRAM II IP use the Altera UniPHY PhY The functional description of each of these modules is described separately so you do not need to read the memory controller functional description if you are creating your own custom memory controller The volume also contains information on how to implement the Ip, including a description of the parameterization GUl, the required constraints, and latency information. The last chapter of this volumc includes timing diagrams showing the memory operations that may help you debug your system or help you create a custom memory controller Simulation, Timing Analysis, and Debugging When vou have implemented your external memory interface, you can use this volume for information on how to perform functional simulation, how to analyze timing, and how to debug your design Implementing a Custom PhY This volume describes the steps to create a custom PHY and offers examples on some custom Phys that are already available for some interfaces Design Flow Tutorials This volume offers step-by-step tutorials in creating a memory interface for specific Altera development boards for debugging and testing. In addition, this volume also discusses special information such as how to implement external memory interfaces using SopC builder or how to implement multiple memory interfaces. The design flow tutorials follow the flow in"Recommended Design Flow"on page 1-1 External Memory Interface Handbook Volume 1 December 2010 Altera Corporation Section L, about this handbook ZAERA 2. Recommended Design Flow This chapter describes the Altcra-recommended design flow for successfully implementing external memory interfaces in Altera devices. Altera recommends that you create an example top-level file with the desired pin outs and all interface IP instantiated, which enables the Quartus ii software to validate your design and resource allocation before PCB and schematic sign off. Use the "Design Checklist"on page 1-6, to verify whether you have performed all the recommended steps in creating a working and robust external memory interface Figure 1-1 shows the design flow to provide the fastest out-of-the-box experience with external memory interfaces in Altera devices. This topic directs you where to find information on how to perform each step of the recommended design flow. The flow assumes that you are using Altera IP to implement the external memory nterface o For design examples that follow the recommended design flow in this chapter, refer to Volume 6: Design Flow Tutorials of the External Memory Interface Handbook December 2010 Altera corporation External Memory Interface Hand book Volume 1 Section l, about this handbook Chapter 2: Recommended Design Flow Figure 2-1. External Memory Interfaces Design Flowchart Start Design Instantiate PHY and Controller Designs Only on Arria Il GX Deter mine bcard and Stratix IV Device SOPC Buiid e Meyawizard Perform board level Simulations Specify Parameters Specify Paramelers Signals Adjust Termination Meet Electrical Complete and Drive Strength Requirements? SOPC Builder System Perform Add Constraints and Functional Simulation Compile Design Simulation Give Verify Timing Daes the esign Have Positive oug Dcs Optional Perfor Verify Desig Ing Simulation Give Debug des Expected Results s Design Working External Memory Interface Handbook Volume 1 December 2010 Altera Corporation Section L, about this handbook

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