axi接口 ddr3

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axi接口 ddr3 xapp739_axi_mpmc
Quick Start R XILINX 4. In ProjNav, select File> Open Project (Figure 2) Fle Edit yiew Project Sou New project open Proje Open Example Project Browser. Copy project close Project Ctrl+N Open Ctrl+o 日 Ctrl+s Save As Print Preview. Pr Ctrl+p ent Files Recent Projects Exit XAFP739_02082911 Figure 2: Opening a Project in Project Navigator 5. Select <design_ dir>/projnav/ m1605 mpmc reference projnav xise and click Open(Figure 3) Open Project Look in:D/proj/mpmc/sandboxed. box/xapp739/projnav++4 O compu D msgs ipcore_dir Ipcore_exam iseconfig ml605-mpmc_reference_projnav xise File name pen Files of type: ISE Project Files (.xise) ÷8 Cancel APP73903091911 Figure 3: Open Project Menu XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX 6. To not rebuild the design but only run the pre-generated bitstream in hardware, skip to step 8. Otherwise, to rebuild the design, continue with these instructions: a. If this is the first time the design is run, the IP cores in the project need to be regenerated. To rebuild the iP cores, select xc6vlx240t-1ff156 in the Hierarchy pane and double-click Design Utilities Regenerate All Cores(Figure 4 Note: If the cores are not regenerated and the design is implemented, Project Navigator prompts the user to regenerate each core( Click Yes for each iP core View. t Implementation O M Simulation Hierarchy g ml605_mpmc_reference_projnav 戴xc6vx240t-1f1156 2 axis_master_example_0_wrapper (ipcore_example/axis_master_exa ro axis_slave_example_0_wrapper (ipcore_example/axis_slave_examp vaa system(system. v) +v DDR3_SDRAM-DDR3_SDRAM (pcore_dir/DDR3_SDRAM/user g clock_generator_1- clock_generator (ipcore_dir/clock_generator. axil_0-axi4 (pcore_dir/axi4xco V axi_vdma_0-vdma (pcore_dir/vdmaxco axivdma- vdma (pcore_dir/vdma xco) y axis_master_example0-axis_master_ example (pcore_example v axis_slave_example_0-axis_slave_example (ipcore_example/a v axilite_master_vdma_o- axi_lite_master_vdma.o (ipcore_exam v axiJite_master_vdma1-axiJJite_master_vdmal (ipcore_exam " t system.ucf C Running: Regenerate All Cores No single design module is selected 多 Design Utilities e Update All Schematic Files e Compile HDL Simulation Libraries Regenerate All Cores Check All Core Versions Start mr Design Files Libraries XAPP7904082911 Figure 4: Regenerating All Cores 7. Build the design to a bitstream using Process Implement Top Module(Figure 5). This step builds the design to a bitstream and might take some time to complete Process Tools Window Layou mplement Top Module ReRu Lt St Run With current Data Force Process Up-to-Date 9r Process Properties XAPP73905082911 igure 5: Implementing a Design in Project Navigator XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX If an error in synthesis occurs with an output message that says unknown module <axi yamas, the workaround for it is a. Close Project Navigator b. Edit <design_ dir>/projnav/m1605 mpmc reference. xise c. find this section of text: <file xil pn: name="ipcore dir/vdma xie xil_ pn: type="FILE_ COREGENISE"> sassociation xil_ pn: name="Implementation"xil_ pn: SecID=237"/> d. Move the above section of text to the top of the file just below the line <files> Note: The seqID value might be different e. Save the text file f. Reopen the text file in Project navigator g. Select Project Cleanup Project Files h. Rebuild the project again The unknown module <axi_vdma> error message should be resolved ML605 Board Setup 8. The reference design runs on the ml605 board shown in Figure 6 Note: Not all ML605 features shown in Figure 6 are referenced or used in this document 0 7b)(70 国c164 5 218 三三三三三 2221a 14 s/ND942-252 (7 (on backside) X73906083011 Figure 6: ML605 Board Photo 9. Connect the USB cable from the host Pc to the USB JTAG port (6 in Figure 6)of the ML605 board to a USB cable(provided with the board) and connect it to the host PC. Ensure that the appropriate device drivers are installed XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX 10. Connect the ML605 DVI connector to a video monitor capable of displaying 1280X720p 60 Hz video signal(14 in Figure 6) 11. Connect the power supply cable to the M605 board (21 c in Figure 6) 12. Turn on the power to the ML605 board( 8a in Figure 6) Download and run bitstream bitstream included in the application note files, perform the followin sing the pre-generated If you have not rebuilt the design and are programming the ML605 using the pre-generated Note: Do not perform this step if the design has already been rebuilt 13. In the Processes window pane, right-click Generate Programming File and select Force Process Up-to-Date(Figure 7). This puts a green check mark next to Generate Programming File and allows iMPACT to be run without building the design Processes: system User Constraints +e Synthesize- XST Implement Design Generate Pro g 多 Configure Targ B 多 Generate Ta ReRun Manage Cor Rerun All cu Analyze Desig star吨 Design Rt Sto View Text Report Force Process Up-to-Date > Implement Top Module Design Goals Strategie vt Process Properties Figure 7: Forcing Generate Programming File Step to be Up-to-Date 14. In Project Navigator, go to the Processes window pane, right-click Configure Target Device and select Run to launch the bitstream download tool iMPACT (Figure 8) Processes: system User Constraint 2 Synthesize·XsT Implement Design CO Generate Pro ogramming file Confi erate Target FI 8 Manage Configura Rerun All eu Analyze Design Usi 贸st Start Bt Design O Files Run With Current Data Implement Top Modul. Design Goals S Strategies 94 Process Properties Figure 8: Launching impact from Project Navigator XAPP739(v1.0)September 23, 2011 www.xilinx.com 6 Quick Start R XILINX 15. Click OK in the Warning window(Figure 9) Warning A No iMPACT project file exists. Click OK to open iMPACT. You will then need to define a configuration chain, designate which device in that chain is the target device, and then save the iMPACT project file Once this step is completed, subsequent runs of the'Configure Target Device' process can program the target device without eding to open the iMPACT GUI OK Figure 9: iMPACT Warning Message 16. The imPACT tool is launched. Select Edit Launch Wizard(Figure 10) Operations Qutput Debug Add Device dit SystemACE Collectio Edit SystemACE Design Edit PFF Revision Ctrl+E Find Next Preferences… APP73910082911 Figure 10: Launching iMPACT Wizard 17. Click OK to start the JTAG scan of the ml605 board( Figure 11) Welcome to iMPACT ple elect an action from the list bel o Configure devices using Boundary-Scan ( JTAG) Automatically connect to a cable and identify Boundary-Scan chain e O Prepare a PROM File O Prepare a System ACE File O Prepare a Boundary-Scan File SVF= OK Cancel igure 11: iMPACT Wizard Welcome Menu XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX 18. Click Yes to auto assign configuration files( Figure 12) Auto Assign Configuration Files Query Dialog Do you want to continue and assign configuration files(s)? Don't show this message again, save the setting in preference ONo (Yes XAPP7912082911 Figure 12: Auto Assign Configuration Files Query Dialog 19. For the first device in the JTAG chain, the SystemAce M interface, click Bypass (Figure 13) Assign New Configuration File Look In 日/ mpmc)sandbox.. c_reference_prajna:90民回国 Computer go a system fifo generator v8 22 ste changdao msgs a system fifo generator v823 ste a auto project xdb system fifo generator v8 2 4 ste axi vdma v3 1 default xdb templates a ipcore dir tm ipcore example a work seconnd xInx auto o xdb pla st roject 1 system fifo generator v821 ste open File name X Cancel Bypass Files of type: All Design Files(*. mpm* bsd) Cance|A‖ Figure 13: Assign New Configuration File(SystemAce Interface) XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX 20. For the Xc6VLX240T device, select system. bit and click Open to load <design_dir>/projnav/system bit to configure the FPGA (Figure 14) Assign New Configuration File Loki:回 mpmc/sandboxes.c_reference_prajna:回 a computer_ngo system fifo generator v8 22 ste khar a msgs system fifo generator v823 ste nadac E auto_project xdI system fifo generator v82 4 ste axi vdma v3 1 default xdb S templates core dir a tmp ipcore example work iseconhig xInx auto o xdb planAhead run_1 xst a system fifo generator v8._ ste open File name system bit X Cancel Bypass les of type: All Design Files (* bit * rbt*nky*.isc* bsd) Cancel al‖ XAPP73914082911 Figure 14: Assign New Configuration File (Xc6VLX240T Device) 21. For SPl or BPI PROM options, click No( Figure 15 Attach SPI or BPI PROM This device supports attached Flash PROMs Do you want to attach an SPl or BPI PRoM to this device? ONO Yes XAPP7c915082911 Figure 15: Attach SPl or BPl PROM Query Dialog XAPP739(v1.0)September 23, 2011 www.xilinx.com Quick Start R XILINX 22. In Device Programming Properties, click OK(Figure 16) Device Programming Properties- Device 2 Programming Properties Category E- Boundary-Scan Device 1( ACECF xccace Property Name Value Device 2( FPGA xc6vlx240t Verify OK Cancel Apply Hel XAFP73916082911 Figure 16: Device Programming Properties Menu 23. Program the FPGA. Right click the xc6vlx 240t device and select Program(Figure 17) IEa &b Eile Edit view Operations Qutput Debug Window Help 口b日00x出"1静3me iMPACT Flows 回回区 pe Boundary Scan 口 SystemACE Create PROM File(PROM File F 口 Web Talk Data Access eFUSE Registers cEvlx24 ot ass system, bit Get Device ID Get Device Signature/Usercode one Step SVF one Step XsVF Read Device D Add SPI/BPI Flash MPACT Processes Assign New Configuration File Available Operations are Set Programming Properties Set Erase Properties E Program eFUSE Registers 命 Read eFUSE Re Launch File Assignment wizard Set Target Device E Set eFUSE Control Register. E Read eFUSE Control Register 命 Get Device ID E Get Device Signature/Usercode E Read Device Status 命 One Step SVF Boundary Scan Console 回 2: Programmed successfully PROCRESS END.End Operation ELapsed time s 27 sec 国 Console@ Errors 4 Warnings Configuration Platform Cable USB 6 MHz XAPP73917C8291 Figure 17: Program FPGA Command in iMPACT XAPP739(v1.0)September 23, 2011 www.xilinx.com 10

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