目 录
目 录
摘 要..........................................................................................................................................................I
ABSTRACT............................................................................................................................................II
目 录.......................................................................................................................................................III
第一章 引 言............................................................................................................................................1
1.1 题背景与发展现状.........................................................................................................................1
1.1.1
课题背景
..................................................................................................................................1
1.1.2 RISC-CPU
的发展现状
............................................................................................................1
1.2 RISC-CPU 优势与现实意义...........................................................................................................1
1.2.1 RISC-CPU
具备的优势
............................................................................................................1
1.2.2
本课题的现实意义
..................................................................................................................2
1.3 本设计的主要内容.........................................................................................................................2
第二章 RISC-CPU 的架构设计.............................................................................................................3
2.1 RISC-CPU 基本架构.......................................................................................................................3
2.2 RISC-CPU 模块的划分...................................................................................................................4
第三章 八位 RISC-CPU 各模块设计与仿真.........................................................................................6
3.1 时钟发生器.....................................................................................................................................6
3.2 指令寄存器.....................................................................................................................................7
3.3 累加器...........................................................................................................................................10
3.4 算术逻辑单元................................................................................................................................11
3.5 数据输出控制器...........................................................................................................................14
3.6 地址多路器...................................................................................................................................15
3.7 程序计数器...................................................................................................................................16
3.8 状态控制器...................................................................................................................................17
第四章 RISC-CPU 的综合及操作时序...............................................................................................25
4.1 RISC-CPU 各模块综合.................................................................................................................25
4.2 CPU 复位启动操作时序...............................................................................................................29
结 论.......................................................................................................................................................30
参考文献.................................................................................................................................................31
致 谢.......................................................................................................................................................32
III
