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<html xmlns="http://www.w3.org/1999/xhtml"><head><meta charset="utf-8"><meta name="generator" content="pdf2htmlEX"><meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/base.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/11457810/raw.css"><script src="https://csdnimg.cn/release/download_crawler_static/js/compatibility.min.js"></script><script src="https://csdnimg.cn/release/download_crawler_static/js/pdf2htmlEX.min.js"></script><script>try{pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({});}catch(e){}</script><title></title></head><body><div id="sidebar" style="display: none"><div id="outline"></div></div><div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/11457810/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">NVM Express</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Revision 1.4 </div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">1 </div><div class="t m0 x1 h2 y6 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y7 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y8 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y9 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 ya ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 yb ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h4 yc ff2 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 h5 yd ff3 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x6 h6 ye ff3 fs3 fc0 sc0 ls3 ws3">NVM Express</div><div class="t m0 x7 h7 yf ff3 fs4 fc0 sc0 ls4 ws4">TM</div><div class="t m0 x8 h6 ye ff3 fs3 fc0 sc0 ls0 ws0"> </div><div class="t m0 x9 h6 y10 ff3 fs3 fc0 sc0 ls3 ws5">Base Specification </div><div class="t m0 x1 h2 y11 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y12 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xa h8 y13 ff2 fs5 fc0 sc0 ls5 ws6">NVM Express </div><div class="t m0 xb h8 y14 ff2 fs5 fc0 sc0 ls6 ws7">Revision 1.4 </div><div class="t m0 xc h8 y15 ff2 fs5 fc0 sc0 ls6 ws8">June 10, 2019 </div><div class="t m0 xd h9 y16 ff4 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xd h9 y17 ff4 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xd h9 y18 ff4 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xd h9 y19 ff4 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xd h9 y1a ff4 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x6 h9 y1b ff4 fs0 fc0 sc0 ls1 wsa">Please send comments to info@nvmexpress.org </div><div class="t m0 x1 h2 y1c ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y1d ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y1e ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 y1f ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div></body></html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/11457810/bg2.jpg"><div class="t m0 xe h2 y1 ff1 fs0 fc0 sc0 ls1 ws1">NVM Express</div><div class="t m0 xf h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x10 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Revision 1.4 </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">2 </div><div class="t m0 x1 h2 y20 ff1 fs0 fc0 sc0 ls1 ws1">NVM Express</div><div class="t m0 x2 h3 y21 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x3 h2 y20 ff1 fs0 fc0 sc0 ls0 ws0"> base specification revision 1.4 is available for download at http://nvmexpress.org. The </div><div class="t m0 x1 h2 y22 ff1 fs0 fc0 sc0 ls1 ws1">NVM Express base specification revision 1.4 incorporates NVM Express base specification revision 1.3, </div><div class="t m0 x1 h2 y23 ff1 fs0 fc0 sc0 ls1 wsa">ratified on April 26, 2017, ECN 001, ECN 002, ECN 003, ECN 004a, ECN 005, ECN 006, TP 4000a, TP </div><div class="t m0 x1 h2 y24 ff1 fs0 fc0 sc0 ls1 wsb">4002, TP 4003c, TP 4004b, TP 4005c, TP 4006, TP 4007a, TP 4008, TP 4014, TP 4016, TP 4018b, TP </div><div class="t m0 x1 h2 y25 ff1 fs0 fc0 sc0 ls1 wsb">4022, TP 4024, TP 4025, TP 4027, TP 4028a, TP 4030, TP 4031a, TP 4032, TP 4033, TP 4035, TP </div><div class="t m0 x1 h2 y26 ff1 fs0 fc0 sc0 ls1 wsb">4039a, TP 4042a, TP 4045, TP 4050, TP 4051, TP 4054, and TP 8002 (refer to </div><div class="t m0 x1 h2 y27 ff1 fs0 fc1 sc0 ls1 wsb">https://nvmexpress.org/changes-in-nvme-revision-1-4 for details). Applied the NVM Express trademark </div><div class="t m0 x1 h2 y28 ff1 fs0 fc0 sc0 ls1 wsa">and logo usage guidelines. </div><div class="t m0 x11 h2 y29 ff1 fs0 fc0 sc0 ls8 wse">SPECIFICATION DISCLAIMER </div><div class="t m0 x1 h4 y2a ff2 fs0 fc0 sc0 ls8 ws2">LEGAL NOTICE: </div><div class="t m0 x1 h4 y2b ff2 fs0 fc0 sc0 lsc ws11">© Copyright 2007 to 2019 NVM Express, Inc. ALL RIGHTS RESERVED. </div><div class="t m0 x1 h2 y2c ff1 fs0 fc0 sc0 ls1 wsa">This NVM Express base specification revision 1.4 is proprietary to the NVM Express, Inc. (also referred to </div><div class="t m0 x1 h2 y2d ff1 fs0 fc0 sc0 ls1 wsa">as “Company”) and/or its successors and assigns. </div><div class="t m0 x1 h4 y2e ff2 fs0 fc0 sc0 ls8 wse">NOTICE TO USERS WHO ARE NVM EXPRESS, INC. MEMBERS: Members of NVM Express, Inc. have </div><div class="t m0 x1 h2 y2f ff1 fs0 fc0 sc0 ls1 wsa">the right to use and implement this NVM Express base specification revision 1.4 subject, however, to the </div><div class="t m0 x1 h2 y30 ff1 fs0 fc0 sc0 ls1 wsa">Member’s continued compliance with the Company’s Intellectual Property Policy and Bylaws and the </div><div class="t m0 x1 h2 y31 ff1 fs0 fc0 sc0 ls1 wsa">Member’s Participation Agreement. </div><div class="t m0 x1 h4 y32 ff2 fs0 fc0 sc0 ls7 wsd">NOTICE TO NON-MEMBERS OF NVM EXPRESS, INC.: If you are not a Member of NVM Express, Inc. </div><div class="t m0 x1 h2 y33 ff1 fs0 fc0 sc0 ls1 wsa">and you have obtained a copy of this document, you only have a right to review this document or make </div><div class="t m0 x1 h2 y34 ff1 fs0 fc0 sc0 ls1 wsa">reference to or cite this document. Any such references or citations to this document must acknowledge </div><div class="t m0 x1 h2 y35 ff1 fs0 fc0 sc0 ls1 wsa">NVM Express, Inc. copyright ownership of this document. The proper copyright citation or reference is as </div><div class="t m0 x1 h4 y36 ff1 fs0 fc0 sc0 ls2 wsc">follows: “© 2007 to 2019 NVM Express, Inc. ALL RIGHTS RESERVED.” When making any such </div><div class="t m0 x1 h2 y37 ff1 fs0 fc0 sc0 ls1 wsa">citations or references to this document you are not permitted to revise, alter, modify, make any </div><div class="t m0 x1 h2 y38 ff1 fs0 fc0 sc0 ls1 wsb">derivatives of, or otherwise amend the referenced portion of this document in any way without the prior </div><div class="t m0 x1 h2 y39 ff1 fs0 fc0 sc0 ls1 wsa">express written permission of NVM Express, Inc. Nothing contained in this document shall be deemed as </div><div class="t m0 x1 h2 y3a ff1 fs0 fc0 sc0 ls1 wsa">granting you any kind of license to implement or use this document or the specification described therein, </div><div class="t m0 x1 h2 y3b ff1 fs0 fc0 sc0 ls1 wsa">or any of its contents, either expressly or impliedly, or to any intellectual property owned or controlled by </div><div class="t m0 x1 h2 y3c ff1 fs0 fc0 sc0 ls1 wsa">NVM Express, Inc., including, without limitation, any trademarks of NVM Express, Inc. </div><div class="t m0 x1 h4 y3d ff2 fs0 fc0 sc0 lse ws16">LEGAL DISCLAIMER: </div><div class="t m0 x1 h4 y3e ff1 fs0 fc0 sc0 ls7 wsd">THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROVIDED ON AN “AS IS” </div><div class="t m0 x1 h2 y3f ff1 fs0 fc0 sc0 ls8 wse">BASIS. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, NVM EXPRESS, INC. </div><div class="t m0 x1 h2 y40 ff1 fs0 fc0 sc0 ls7 wsd">(ALONG WITH THE CONTRIBUTORS TO THIS DOCUMENT) HEREBY DISCLAIM ALL </div><div class="t m0 x1 h2 y41 ff1 fs0 fc0 sc0 ls8 wse">REPRESENTATIONS, WARRANTIES AND/OR COVENANTS, EITHER EXPRESS OR IMPLIED, </div><div class="t m0 x1 h2 y42 ff1 fs0 fc0 sc0 ls7 wsd">STATUTORY OR AT COMMON LAW, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED </div><div class="t m0 x1 h2 y43 ff1 fs0 fc0 sc0 ls8 wse">WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, VALIDITY, </div><div class="t m0 x1 h2 y44 ff1 fs0 fc0 sc0 ls7 wsd">AND/OR NONINFRINGEMENT. </div><div class="t m0 x1 h2 y45 ff1 fs0 fc0 sc0 ls1 wsa">All product names, trademarks, registered trademarks, and/or servicemarks may be claimed as the </div><div class="t m0 x1 h2 y46 ff1 fs0 fc0 sc0 ls1 wsa">property of their respective owners. </div><div class="t m0 x1 h2 y47 ff1 fs0 fc0 sc0 ls1 wsa">The NVM Express</div><div class="t m0 x12 h3 y48 ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x13 h2 y49 ff1 fs0 fc0 sc0 ls0 ws0"> design mark is a registered trademark of NVM Express, Inc. </div><div class="t m0 x1 h2 y4a ff1 fs0 fc0 sc0 ls8 ws2">PCI-SIG</div><div class="t m0 x14 h3 y4b ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x15 h2 y4c ff1 fs0 fc0 sc0 ls0 ws0"> and PCIe</div><div class="t m0 x13 h3 y4b ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x16 h2 y4c ff1 fs0 fc0 sc0 ls0 ws0"> are registered trademarks of PCI-SIG. </div><div class="t m0 x1 h2 y4d ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x17 h2 y4e ff1 fs0 fc0 sc0 ls1 ws19">NVM Express Workgroup </div><div class="t m0 x17 h2 y4f ff1 fs0 fc0 sc0 ls1 wsa">c/o VTM, Inc. </div><div class="t m0 x17 h2 y50 ff1 fs0 fc0 sc0 ls1 wsa">3855 SW 153</div><div class="t m0 x18 h3 y51 ff1 fs1 fc0 sc0 ls0 ws0">rd</div><div class="t m0 x19 h2 y52 ff1 fs0 fc0 sc0 ls0 ws0"> Drive </div><div class="t m0 x17 h2 y53 ff1 fs0 fc0 sc0 ls1 wsa">Beaverton, OR 97003 USA </div><div class="t m0 x17 h2 y54 ff1 fs0 fc0 sc0 ls1 wsb">info@nvmexpress.org </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/11457810/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">NVM Express</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Revision 1.4 </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1a h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m0 x1b ha y55 ff2 fs6 fc0 sc0 ls12 ws1c">Table of Contents </div><div class="t m0 x1 hb y56 ff3 fs0 fc0 sc0 ls0 ws0">1 INTRODUCTION ............................................................................................................. 6 </div><div class="t m0 x1c h2 y57 ff1 fs0 fc0 sc0 ls1 wsb">1.1 Overview ........................................................................................................................................ 6 </div><div class="t m0 x1c h2 y58 ff1 fs0 fc0 sc0 ls1 wsb">1.2 Scope............................................................................................................................................. 6 </div><div class="t m0 x1c h2 y59 ff1 fs0 fc0 sc0 ls1 wsb">1.3 Outside of Scope ........................................................................................................................... 6 </div><div class="t m0 x1c h2 y5a ff1 fs0 fc0 sc0 ls1 wsb">1.4 Theory of Operation ....................................................................................................................... 7 </div><div class="t m0 x1c h2 y5b ff1 fs0 fc0 sc0 ls1 wsb">1.5 Conventions ................................................................................................................................. 12 </div><div class="t m0 x1c h2 y5c ff1 fs0 fc0 sc0 ls1 wsb">1.6 Definitions .................................................................................................................................... 13 </div><div class="t m0 x1c h2 y5d ff1 fs0 fc0 sc0 ls1 wsb">1.7 Keywords ..................................................................................................................................... 18 </div><div class="t m0 x1c h2 y5e ff1 fs0 fc0 sc0 ls1 wsb">1.8 Byte, Word, and Dword Relationships ......................................................................................... 19 </div><div class="t m0 x1c h2 y5f ff1 fs0 fc0 sc0 ls1 wsb">1.9 References .................................................................................................................................. 19 </div><div class="t m0 x1c h2 y60 ff1 fs0 fc0 sc0 ls1 wsb">1.10 References Under Development ................................................................................................. 20 </div><div class="t m0 x1 hb y61 ff3 fs0 fc0 sc0 ls0 ws0">2 SYSTEM BUS (PCI EXPRESS) REGISTERS ....................................................................... 21 </div><div class="t m0 x1c h2 y62 ff1 fs0 fc0 sc0 ls1 wsb">2.1 PCI Header .................................................................................................................................. 21 </div><div class="t m0 x1c h2 y63 ff1 fs0 fc0 sc0 ls1 wsb">2.2 PCI Power Management Capabilities .......................................................................................... 26 </div><div class="t m0 x1c h2 y64 ff1 fs0 fc0 sc0 ls1 wsb">2.3 Message Signaled Interrupt Capability (Optional) ....................................................................... 28 </div><div class="t m0 x1c h2 y65 ff1 fs0 fc0 sc0 ls1 wsb">2.4 MSI-X Capability (Optional) ......................................................................................................... 29 </div><div class="t m0 x1c h2 y66 ff1 fs0 fc0 sc0 ls1 wsb">2.5 PCI Express Capability ................................................................................................................ 31 </div><div class="t m0 x1c h2 y67 ff1 fs0 fc0 sc0 ls1 wsb">2.6 Advanced Error Reporting Capability (Optional) ......................................................................... 36 </div><div class="t m0 x1c h2 y68 ff1 fs0 fc0 sc0 ls1 wsb">2.7 Other Capability Pointers............................................................................................................. 41 </div><div class="t m0 x1 hb y69 ff3 fs0 fc0 sc0 ls0 ws0">3 CONTROLLER REGISTERS ............................................................................................. 42 </div><div class="t m0 x1c h2 y6a ff1 fs0 fc0 sc0 ls1 wsb">3.1 Register Definition ....................................................................................................................... 42 </div><div class="t m0 x1c h2 y6b ff1 fs0 fc0 sc0 ls1 wsb">3.2 Index/Data Pair registers (Optional) ............................................................................................ 61 </div><div class="t m0 x1 hb y6c ff3 fs0 fc0 sc0 ls0 ws0">4 DATA STRUCTURES ..................................................................................................... 63 </div><div class="t m0 x1c h2 y6d ff1 fs0 fc0 sc0 ls1 wsb">4.1 Submission Queue & Completion Queue Definition ................................................................... 63 </div><div class="t m0 x1c h2 y6e ff1 fs0 fc0 sc0 ls1 wsb">4.2 Submission Queue Entry – Command Format ........................................................................... 65 </div><div class="t m0 x1c h2 y6f ff1 fs0 fc0 sc0 ls1 wsb">4.3 Physical Region Page Entry and List .......................................................................................... 69 </div><div class="t m0 x1c h2 y70 ff1 fs0 fc0 sc0 ls1 wsb">4.4 Scatter Gather List (SGL) ............................................................................................................ 70 </div><div class="t m0 x1c h2 y71 ff1 fs0 fc0 sc0 ls1 wsb">4.5 Metadata Region (MR) ................................................................................................................ 76 </div><div class="t m0 x1c h2 y72 ff1 fs0 fc0 sc0 ls1 wsb">4.6 Completion Queue Entry ............................................................................................................. 77 </div><div class="t m0 x1c h2 y73 ff1 fs0 fc0 sc0 ls1 wsb">4.7 Controller Memory Buffer ............................................................................................................ 85 </div><div class="t m0 x1c h2 y74 ff1 fs0 fc0 sc0 ls1 wsb">4.8 Persistent Memory Region .......................................................................................................... 86 </div><div class="t m0 x1c h2 y75 ff1 fs0 fc0 sc0 ls1 wsb">4.9 NVM Sets .................................................................................................................................... 88 </div><div class="t m0 x1c h2 y76 ff1 fs0 fc0 sc0 ls1 wsb">4.10 Namespace List ........................................................................................................................... 89 </div><div class="t m0 x1c h2 y77 ff1 fs0 fc0 sc0 ls1 wsb">4.11 Controller List .............................................................................................................................. 90 </div><div class="t m0 x1c h2 y78 ff1 fs0 fc0 sc0 ls1 wsb">4.12 Fused Operations ........................................................................................................................ 90 </div><div class="t m0 x1c h2 y79 ff1 fs0 fc0 sc0 ls1 wsb">4.13 Command Arbitration ................................................................................................................... 91 </div><div class="t m0 x1 hb y7a ff3 fs0 fc0 sc0 ls0 ws0">5 ADMIN COMMAND SET ................................................................................................. 94 </div><div class="t m0 x1c h2 y7b ff1 fs0 fc0 sc0 ls1 wsb">5.1 Abort command ........................................................................................................................... 95 </div><div class="t m0 x1c h2 y7c ff1 fs0 fc0 sc0 ls1 wsb">5.2 Asynchronous Event Request command .................................................................................... 96 </div><div class="t m0 x1c h2 y7d ff1 fs0 fc0 sc0 ls1 wsb">5.3 Create I/O Completion Queue command .................................................................................. 101 </div><div class="t m0 x1c h2 y7e ff1 fs0 fc0 sc0 ls1 wsb">5.4 Create I/O Submission Queue command.................................................................................. 102 </div><div class="t m0 x1c h2 y7f ff1 fs0 fc0 sc0 ls1 wsb">5.5 Delete I/O Completion Queue command .................................................................................. 105 </div><div class="t m0 x1c h2 y80 ff1 fs0 fc0 sc0 ls1 wsb">5.6 Delete I/O Submission Queue command .................................................................................. 105 </div><div class="t m0 x1c h2 y81 ff1 fs0 fc0 sc0 ls1 wsb">5.7 Doorbell Buffer Config command .............................................................................................. 106 </div><div class="t m0 x1c h2 y82 ff1 fs0 fc0 sc0 ls1 wsb">5.8 Device Self-test command ........................................................................................................ 107 </div><div class="t m0 x1c h2 y83 ff1 fs0 fc0 sc0 ls1 wsb">5.9 Directive Receive command ...................................................................................................... 109 </div><div class="t m0 x1c h2 y84 ff1 fs0 fc0 sc0 ls1 wsb">5.10 Directive Send command .......................................................................................................... 110 </div><div class="t m0 x1c h2 y85 ff1 fs0 fc0 sc0 ls1 wsb">5.11 Firmware Commit command ..................................................................................................... 111 </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/11457810/bg4.jpg"><div class="t m0 xe h2 y1 ff1 fs0 fc0 sc0 ls1 ws1">NVM Express</div><div class="t m0 xf h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x10 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Revision 1.4 </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x4 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">4 </div><div class="t m0 x1c h2 y20 ff1 fs0 fc0 sc0 ls1 wsb">5.12 Firmware Image Download command ....................................................................................... 113 </div><div class="t m0 x1c h2 y86 ff1 fs0 fc0 sc0 ls1 wsb">5.13 Get Features command ............................................................................................................. 114 </div><div class="t m0 x1c h2 y87 ff1 fs0 fc0 sc0 ls1 wsb">5.14 Get Log Page command............................................................................................................ 117 </div><div class="t m0 x1c h2 y88 ff1 fs0 fc0 sc0 ls1 wsb">5.15 Identify command ...................................................................................................................... 161 </div><div class="t m0 x1c h2 y89 ff1 fs0 fc0 sc0 ls1 wsb">5.16 Keep Alive command ................................................................................................................. 201 </div><div class="t m0 x1c h2 y8a ff1 fs0 fc0 sc0 ls1 wsb">5.17 NVMe-MI Receive command .................................................................................................... 201 </div><div class="t m0 x1c h2 y8b ff1 fs0 fc0 sc0 ls1 wsb">5.18 NVMe-MI Send command ......................................................................................................... 201 </div><div class="t m0 x1c h2 y8c ff1 fs0 fc0 sc0 ls1 wsb">5.19 Namespace Attachment command ........................................................................................... 201 </div><div class="t m0 x1c h2 y8d ff1 fs0 fc0 sc0 ls1 wsb">5.20 Namespace Management command ........................................................................................ 202 </div><div class="t m0 x1c h2 y8e ff1 fs0 fc0 sc0 ls1 wsb">5.21 Set Features command ............................................................................................................. 205 </div><div class="t m0 x1c h2 y8f ff1 fs0 fc0 sc0 ls1 wsb">5.22 Virtualization Management command ....................................................................................... 232 </div><div class="t m0 x1c h2 y90 ff1 fs0 fc0 sc0 ls1 wsb">5.23 Format NVM command – NVM Command Set Specific ........................................................... 234 </div><div class="t m0 x1c h2 y91 ff1 fs0 fc0 sc0 ls1 wsb">5.24 Sanitize command – NVM Command Set Specific ................................................................... 236 </div><div class="t m0 x1c h2 y92 ff1 fs0 fc0 sc0 ls1 wsb">5.25 Security Receive command – NVM Command Set Specific ..................................................... 239 </div><div class="t m0 x1c h2 y93 ff1 fs0 fc0 sc0 ls1 wsb">5.26 Security Send command – NVM Command Set Specific ......................................................... 240 </div><div class="t m0 x1c h2 y94 ff1 fs0 fc0 sc0 ls1 wsb">5.27 Get LBA Status command – NVM Command Set Specific ....................................................... 241 </div><div class="t m0 x1 hb y95 ff3 fs0 fc0 sc0 ls0 ws0">6 NVM COMMAND SET ................................................................................................. 245 </div><div class="t m0 x1c h2 y96 ff1 fs0 fc0 sc0 ls1 wsb">6.1 Namespaces .............................................................................................................................. 246 </div><div class="t m0 x1c h2 y97 ff1 fs0 fc0 sc0 ls1 wsb">6.2 Fused Operations ...................................................................................................................... 248 </div><div class="t m0 x1c h2 y98 ff1 fs0 fc0 sc0 ls1 wsb">6.3 Command Ordering Requirements ........................................................................................... 249 </div><div class="t m0 x1c h2 y99 ff1 fs0 fc0 sc0 ls1 wsb">6.4 Atomic Operations ..................................................................................................................... 249 </div><div class="t m0 x1c h2 y9a ff1 fs0 fc0 sc0 ls1 wsb">6.5 End-to-end Protection Information ............................................................................................ 253 </div><div class="t m0 x1c h2 y9b ff1 fs0 fc0 sc0 ls1 wsb">6.6 Compare command ................................................................................................................... 253 </div><div class="t m0 x1c h2 y9c ff1 fs0 fc0 sc0 ls1 wsb">6.7 Dataset Management command ............................................................................................... 255 </div><div class="t m0 x1c h2 y9d ff1 fs0 fc0 sc0 ls1 wsb">6.8 Flush command ......................................................................................................................... 258 </div><div class="t m0 x1c h2 y9e ff1 fs0 fc0 sc0 ls1 wsb">6.9 Read command ......................................................................................................................... 258 </div><div class="t m0 x1c h2 y9f ff1 fs0 fc0 sc0 ls1 wsb">6.10 Reservation Acquire command ................................................................................................. 261 </div><div class="t m0 x1c h2 ya0 ff1 fs0 fc0 sc0 ls1 wsb">6.11 Reservation Register command ................................................................................................ 262 </div><div class="t m0 x1c h2 ya1 ff1 fs0 fc0 sc0 ls1 wsb">6.12 Reservation Release command ................................................................................................ 263 </div><div class="t m0 x1c h2 ya2 ff1 fs0 fc0 sc0 ls1 wsb">6.13 Reservation Report command ................................................................................................... 264 </div><div class="t m0 x1c h2 ya3 ff1 fs0 fc0 sc0 ls1 wsb">6.14 Verify command ......................................................................................................................... 267 </div><div class="t m0 x1c h2 ya4 ff1 fs0 fc0 sc0 ls1 wsb">6.15 Write command ......................................................................................................................... 268 </div><div class="t m0 x1c h2 ya5 ff1 fs0 fc0 sc0 ls1 wsb">6.16 Write Uncorrectable command .................................................................................................. 271 </div><div class="t m0 x1c h2 ya6 ff1 fs0 fc0 sc0 ls1 wsb">6.17 Write Zeroes command ............................................................................................................. 272 </div><div class="t m0 x1 hb ya7 ff3 fs0 fc0 sc0 ls0 ws0">7 CONTROLLER ARCHITECTURE ..................................................................................... 274 </div><div class="t m0 x1c h2 ya8 ff1 fs0 fc0 sc0 ls1 wsb">7.1 Introduction ................................................................................................................................ 274 </div><div class="t m0 x1c h2 ya9 ff1 fs0 fc0 sc0 ls1 wsb">7.2 Command Submission and Completion Mechanism (Informative) ........................................... 283 </div><div class="t m0 x1c h2 yaa ff1 fs0 fc0 sc0 ls1 wsb">7.3 Resets........................................................................................................................................ 290 </div><div class="t m0 x1c h2 yab ff1 fs0 fc0 sc0 ls1 wsb">7.4 Queue Management .................................................................................................................. 291 </div><div class="t m0 x1c h2 yac ff1 fs0 fc0 sc0 ls1 wsb">7.5 Interrupts ................................................................................................................................... 292 </div><div class="t m0 x1c h2 yad ff1 fs0 fc0 sc0 ls1 wsb">7.6 Controller Initialization and Shutdown Processing .................................................................... 295 </div><div class="t m0 x1c h2 yae ff1 fs0 fc0 sc0 ls1 wsb">7.7 Asynchronous Event Request Host Software Recommendations (Informative) ....................... 297 </div><div class="t m0 x1c h2 yaf ff1 fs0 fc0 sc0 ls1 wsb">7.8 Feature Values .......................................................................................................................... 298 </div><div class="t m0 x1c h2 yb0 ff1 fs0 fc0 sc0 ls1 wsb">7.9 NVMe Qualified Names ............................................................................................................. 299 </div><div class="t m0 x1c h2 y7d ff1 fs0 fc0 sc0 ls1 wsb">7.10 Identifier Format and Layout (Informative) ................................................................................ 300 </div><div class="t m0 x1c h2 yb1 ff1 fs0 fc0 sc0 ls1 wsb">7.11 Unique Identifier ........................................................................................................................ 303 </div><div class="t m0 x1c h2 yb2 ff1 fs0 fc0 sc0 ls1 wsb">7.12 Keep Alive ................................................................................................................................. 304 </div><div class="t m0 x1c h2 yb3 ff1 fs0 fc0 sc0 ls1 wsb">7.13 Updating Controller Doorbell Registers using a Shadow Doorbell Buffer ................................. 306 </div><div class="t m0 x1c h2 yb4 ff1 fs0 fc0 sc0 ls1 wsb">7.14 Privileged Actions ...................................................................................................................... 306 </div><div class="t m0 x1 hb yb5 ff3 fs0 fc0 sc0 ls0 ws0">8 FEATURES ................................................................................................................ 307 </div><div class="t m0 x1c h2 yb6 ff1 fs0 fc0 sc0 ls1 wsb">8.1 Firmware Update Process ......................................................................................................... 307 </div><div class="t m0 x1c h2 yb7 ff1 fs0 fc0 sc0 ls1 wsb">8.2 Metadata Handling .................................................................................................................... 308 </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/11457810/bg5.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">NVM Express</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">TM</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Revision 1.4 </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1a h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m0 x1c h2 y20 ff1 fs0 fc0 sc0 ls1 wsb">8.3 End-to-end Data Protection (Optional) ...................................................................................... 309 </div><div class="t m0 x1c h2 y86 ff1 fs0 fc0 sc0 ls1 wsb">8.4 Power Management .................................................................................................................. 315 </div><div class="t m0 x1c h2 y87 ff1 fs0 fc0 sc0 ls1 wsb">8.5 Virtualization Enhancements (Optional) .................................................................................... 320 </div><div class="t m0 x1c h2 y88 ff1 fs0 fc0 sc0 ls1 wsb">8.6 Doorbell Stride for Software Emulation ..................................................................................... 325 </div><div class="t m0 x1c h2 y89 ff1 fs0 fc0 sc0 ls1 wsb">8.7 Standard Vendor Specific Command Format ........................................................................... 325 </div><div class="t m0 x1c h2 y8a ff1 fs0 fc0 sc0 ls1 wsb">8.8 Reservations (Optional) ............................................................................................................. 325 </div><div class="t m0 x1c h2 y8b ff1 fs0 fc0 sc0 ls1 wsb">8.9 Host Memory Buffer (Optional) .................................................................................................. 332 </div><div class="t m0 x1c h2 y8c ff1 fs0 fc0 sc0 ls1 wsb">8.10 Replay Protected Memory Block (Optional) .............................................................................. 333 </div><div class="t m0 x1c h2 y8d ff1 fs0 fc0 sc0 ls1 wsb">8.11 Device Self-test Operations (Optional) ...................................................................................... 345 </div><div class="t m0 x1c h2 y8e ff1 fs0 fc0 sc0 ls1 wsb">8.12 Namespace Management (Optional) ........................................................................................ 347 </div><div class="t m0 x1c h2 y8f ff1 fs0 fc0 sc0 ls1 wsb">8.13 Boot Partitions (Optional) .......................................................................................................... 349 </div><div class="t m0 x1c h2 y90 ff1 fs0 fc0 sc0 ls1 wsb">8.14 Telemetry (Optional) .................................................................................................................. 352 </div><div class="t m0 x1c h2 y91 ff1 fs0 fc0 sc0 ls1 wsb">8.15 Sanitize Operations (Optional) .................................................................................................. 356 </div><div class="t m0 x1c h2 y92 ff1 fs0 fc0 sc0 ls1 wsb">8.16 Read Recovery Level (Optional) ............................................................................................... 360 </div><div class="t m0 x1c h2 y93 ff1 fs0 fc0 sc0 ls1 wsb">8.17 Endurance Groups .................................................................................................................... 362 </div><div class="t m0 x1c h2 y94 ff1 fs0 fc0 sc0 ls1 wsb">8.18 Predictable Latency Mode (Optional) ........................................................................................ 363 </div><div class="t m0 x1c h2 yb8 ff1 fs0 fc0 sc0 ls1 wsb">8.19 Namespace Write Protection (Optional) .................................................................................... 367 </div><div class="t m0 x1c h2 yb9 ff1 fs0 fc0 sc0 ls1 wsb">8.20 Asymmetric Namespace Access Reporting (Optional) ............................................................. 369 </div><div class="t m0 x1c h2 yba ff1 fs0 fc0 sc0 ls1 wsb">8.21 Host Operation with Asymmetric Namespace Access Reporting (Informative) ........................ 376 </div><div class="t m0 x1c h2 ybb ff1 fs0 fc0 sc0 ls1 wsb">8.22 Get LBA Status .......................................................................................................................... 378 </div><div class="t m0 x1c h2 ybc ff1 fs0 fc0 sc0 ls1 wsb">8.23 SQ Associations (Optional) ....................................................................................................... 381 </div><div class="t m0 x1c h2 ybd ff1 fs0 fc0 sc0 ls1 wsb">8.24 UUIDs for Vendor Specific Information ..................................................................................... 381 </div><div class="t m0 x1c h2 ybe ff1 fs0 fc0 sc0 ls1 wsb">8.25 Improving Performance through I/O Size and Alignment Adherence ....................................... 384 </div><div class="t m0 x1 hb ybf ff3 fs0 fc0 sc0 ls0 ws0">9 DIRECTIVES.............................................................................................................. 390 </div><div class="t m0 x1c h2 y9d ff1 fs0 fc0 sc0 ls1 wsb">9.1 Directive Use in I/O Commands ................................................................................................ 390 </div><div class="t m0 x1c h2 y9e ff1 fs0 fc0 sc0 ls1 wsb">9.2 Identify (Directive Type 00h) ..................................................................................................... 391 </div><div class="t m0 x1c h2 y9f ff1 fs0 fc0 sc0 ls1 wsb">9.3 Streams (Directive Type 01h, Optional) .................................................................................... 393 </div><div class="t m0 x1 hb yc0 ff3 fs0 fc0 sc0 ls8 ws2">10 ERROR REPORTING AND RECOVERY .......................................................................... 400 </div><div class="t m0 x1c h2 yc1 ff1 fs0 fc0 sc0 ls1 wsb">10.1 Command and Queue Error Handling ....................................................................................... 400 </div><div class="t m0 x1c h2 yc2 ff1 fs0 fc0 sc0 ls1 wsb">10.2 Media and Data Error Handling ................................................................................................. 400 </div><div class="t m0 x1c h2 yc3 ff1 fs0 fc0 sc0 ls1 wsb">10.3 Memory Error Handling ............................................................................................................. 400 </div><div class="t m0 x1c h2 yc4 ff1 fs0 fc0 sc0 ls1 wsb">10.4 Internal Controller Error Handling .............................................................................................. 400 </div><div class="t m0 x1c h2 yc5 ff1 fs0 fc0 sc0 ls1 wsb">10.5 Controller Fatal Status Condition .............................................................................................. 401 </div><div class="t m0 x1 hb yc6 ff3 fs0 fc0 sc0 ls0 ws0">ANNEX A. SANITIZE OPERATION CONSIDERATIONS (INFORMATIVE) ..................................... 402 </div><div class="t m0 x1c h2 yc7 ff1 fs0 fc0 sc0 ls8 ws2">A.1 Overview .................................................................................................................................... 402 </div><div class="t m0 x1c h2 yc8 ff1 fs0 fc0 sc0 ls8 ws2">A.2 Hidden Storage (Overprovisioning) ........................................................................................... 402 </div><div class="t m0 x1c h2 yc9 ff1 fs0 fc0 sc0 ls8 ws2">A.3 Integrity checks and No-Deallocate After Sanitize .................................................................... 402 </div><div class="t m0 x1c h2 yca ff1 fs0 fc0 sc0 ls8 ws2">A.4 Bad Block and Vendor Specific NAND Use .............................................................................. 402 </div><div class="t m0 x1 h2 ycb ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x1 h2 ycc ff1 fs0 fc0 sc0 ls0 ws0"> </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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