Section number Title Page
3.2 Signals overview...........................................................................................................................................................99
3.3 Configuration signals sampled at reset.........................................................................................................................109
3.4 Output signal states during reset...................................................................................................................................111
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview.......................................................................................................................................................................113
4.2 External signal descriptions..........................................................................................................................................113
4.2.1 System control signals...............................................................................................................................114
4.2.2 Clock signals..............................................................................................................................................115
4.3 Accessing configuration, control, and status registers..................................................................................................116
4.3.1 Updating CCSRBAR.................................................................................................................................116
4.3.2 Accessing alternate configuration space....................................................................................................117
4.3.3 Boot page translation.................................................................................................................................117
4.3.4 Boot sequencer...........................................................................................................................................118
4.4 Reset memory map/register definition..........................................................................................................................118
4.4.1 Configuration, control, and status registers base address register (Reset_CCSRBAR)............................119
4.4.2 Alternate configuration base address register (Reset_ALTCBAR)...........................................................119
4.4.3 Alternate configuration attribute register (Reset_ALTCAR)....................................................................120
4.4.4 Boot page translation register (Reset_BPTR)............................................................................................121
4.5 Functional description...................................................................................................................................................121
4.5.1 Reset operations.........................................................................................................................................121
4.5.1.1 Soft reset................................................................................................................................122
4.5.1.2 Hard reset...............................................................................................................................122
4.5.2 Power-on reset sequence............................................................................................................................122
4.5.3 Power-on reset configuration.....................................................................................................................124
4.5.3.1 System PLL ratio...................................................................................................................125
4.5.3.2 DDR PLL ratio.......................................................................................................................125
4.5.3.3 e500 core PLL ratios..............................................................................................................126
4.5.3.4 Core speed..............................................................................................................................126
P1014 QorIQ Integrated Processor Reference Manual, Rev. 2, 11/2012
Freescale Semiconductor, Inc. 5
