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P1014 QorIQ Integrated Processor
Reference Manual
Document Number: P1014RM
Rev. 2, 11/2012
P1014 QorIQ Integrated Processor Reference Manual, Rev. 2, 11/2012
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
Overview
1.1 Overview.......................................................................................................................................................................65
1.1.1 Block diagram............................................................................................................................................65
1.1.2 Critical performance parameters................................................................................................................66
1.1.3 Chip-level features.....................................................................................................................................66
1.2 Application examples....................................................................................................................................................67
1.2.1 Media server/NAS......................................................................................................................................68
1.2.2 Low-end voice gateway.............................................................................................................................69
1.2.3 Wireless LAN router..................................................................................................................................70
1.3 Architecture overview...................................................................................................................................................71
1.3.1 e500v2 core and memory unit....................................................................................................................72
1.3.2 Enhanced three-speed Ethernet controllers................................................................................................72
1.3.3 Programmable interrupt controller.............................................................................................................73
1.3.4 DDR3/DDR3L memory controller............................................................................................................74
1.3.5 High-speed I/O interfaces..........................................................................................................................74
1.3.5.1 PCI Express interfaces...........................................................................................................74
1.3.5.2 SGMII....................................................................................................................................74
1.3.5.3 Dual serial ATA (SATA) controllers.....................................................................................75
1.3.5.4 High-speed interface multiplexing.........................................................................................75
1.3.6 Security engine...........................................................................................................................................76
1.3.7 TDM interface............................................................................................................................................76
1.3.8 Enhanced secure digital host controller (eSDHC).....................................................................................77
1.3.9 Universal serial bus (USB) 2.0..................................................................................................................77
1.3.10 DMA, I2C, DUART, and integrated flash controller................................................................................77
1.3.11 Boot sequencer...........................................................................................................................................78
1.3.12 Device performance monitor.....................................................................................................................78
P1014 QorIQ Integrated Processor Reference Manual, Rev. 2, 11/2012
Freescale Semiconductor, Inc. 3
Section number Title Page
Chapter 2
Memory Map
2.1 Overview.......................................................................................................................................................................79
2.2 Configuration, control, and status registers..................................................................................................................80
2.2.1 Accessing CCSR memory from the local processor..................................................................................81
2.2.2 Accessing CCSR memory from external masters......................................................................................81
2.2.3 Organization of CCSR space.....................................................................................................................82
2.2.3.1 General utilities registers.......................................................................................................82
2.2.3.1.1 General utilities register organization.............................................................83
2.2.3.2 Programmable interrupt controller registers..........................................................................84
2.2.3.3 Device-specific utilities registers...........................................................................................85
2.2.4 CCSR address map.....................................................................................................................................86
2.3 Local access windows...................................................................................................................................................88
2.3.1 Precedence of local access windows..........................................................................................................89
2.3.2 Configuring local access windows.............................................................................................................89
2.3.3 Distinguishing local access windows from other mapping functions........................................................90
2.3.4 Illegal interaction between local access windows and DDR chip selects..................................................90
2.3.5 Local address map example.......................................................................................................................90
2.4 Local access window registers......................................................................................................................................92
2.4.1 Local access window n base address register (LAW_LAWBARn)..........................................................93
2.4.2 Local access window n attribute register (LAW_LAWARn)....................................................................93
2.5 Address translation and mapping units.........................................................................................................................95
2.5.1 Address translation.....................................................................................................................................95
2.5.2 Outbound ATMUs.....................................................................................................................................96
2.5.3 Inbound ATMUs........................................................................................................................................96
2.5.3.1 Illegal interaction between inbound ATMUs and LAWs......................................................97
Chapter 3
Signal Descriptions
3.1 Introduction...................................................................................................................................................................99
P1014 QorIQ Integrated Processor Reference Manual, Rev. 2, 11/2012
4 Freescale Semiconductor, Inc.
Section number Title Page
3.2 Signals overview...........................................................................................................................................................99
3.3 Configuration signals sampled at reset.........................................................................................................................109
3.4 Output signal states during reset...................................................................................................................................111
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview.......................................................................................................................................................................113
4.2 External signal descriptions..........................................................................................................................................113
4.2.1 System control signals...............................................................................................................................114
4.2.2 Clock signals..............................................................................................................................................115
4.3 Accessing configuration, control, and status registers..................................................................................................116
4.3.1 Updating CCSRBAR.................................................................................................................................116
4.3.2 Accessing alternate configuration space....................................................................................................117
4.3.3 Boot page translation.................................................................................................................................117
4.3.4 Boot sequencer...........................................................................................................................................118
4.4 Reset memory map/register definition..........................................................................................................................118
4.4.1 Configuration, control, and status registers base address register (Reset_CCSRBAR)............................119
4.4.2 Alternate configuration base address register (Reset_ALTCBAR)...........................................................119
4.4.3 Alternate configuration attribute register (Reset_ALTCAR)....................................................................120
4.4.4 Boot page translation register (Reset_BPTR)............................................................................................121
4.5 Functional description...................................................................................................................................................121
4.5.1 Reset operations.........................................................................................................................................121
4.5.1.1 Soft reset................................................................................................................................122
4.5.1.2 Hard reset...............................................................................................................................122
4.5.2 Power-on reset sequence............................................................................................................................122
4.5.3 Power-on reset configuration.....................................................................................................................124
4.5.3.1 System PLL ratio...................................................................................................................125
4.5.3.2 DDR PLL ratio.......................................................................................................................125
4.5.3.3 e500 core PLL ratios..............................................................................................................126
4.5.3.4 Core speed..............................................................................................................................126
P1014 QorIQ Integrated Processor Reference Manual, Rev. 2, 11/2012
Freescale Semiconductor, Inc. 5
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