EDA jiaotong dengkongzhi

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS
   PORT(CLK,SM,SB:IN BIT;
        MR,MY,MG,BR,BY,BG:OUT BIT);
END JTDKZ;
ARCHITECTURE ART OF JTDKZ IS
  TYPE STATE_TYPE IS (A,B,C,D);
  SIGNAL STATE:STATE_TYPE;
  BEGIN
CNT:PROCESS(CLK)
VARIABLE S:INTEGER RANGE 0 TO 29;
VARIABLE CLR,EN:BIT;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
   IF CLR='0' THEN S:=0;
    ELSIF EN='0' THEN S:=1;
    ELSE S:=S+1;
   END IF;
CASE STATE IS
   WHEN A=>MR<='0';MY<='0';MG<='1';
   BR<='1';BY<='0';BG<='0';
IF(SB AND SM)='1' THEN 
IF S=29 THEN 
STATE<=B;CLR:='0';EN:='0';
     ELSE 
      STATE<=A;CLR:='1';EN:='1';
     END IF;
ELSIF(SB AND(NOT SM))='1' THEN