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xilinx的jtag2axi databook
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文档给出了xilinx的jtag2axi master的IP的使用及生成 databook
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JTAG to AXI Master
v1.2
LogiCORE IP Product Guide
Vivado Design Suite
PG174 February 4, 2021
JTAG to AXI Master v1.2 2
PG174 February 4, 2021 www.xilinx.com
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 5: Example Design
Creating AXI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Issuing AXI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
<component name>_example/<component name>_example.srcs/ . . . . . . . . . . . . . . . . . . . . . . . . 22
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JTAG to AXI Master v1.2 3
PG174 February 4, 2021 www.xilinx.com
Chapter 6: Test Bench
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix C: Additional Resources and Legal Noticesa
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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JTAG to AXI Master v1.2 4
PG174 February 4, 2021 www.xilinx.com Product Specification
Introduction
The LogiCORE™ JTAG to AXI Master IP core is a
customizable core that can generate the AXI
transactions and drive the AXI signals internal
to the FPGA in the system. The AXI bus
interface protocol can be selected using a
parameter in the IP customization Vivado
®
Integrated Design Environment (IDE). The width
of the AXI data bus is customizable. This IP can
drive AXI4-Lite or AXI4 Memory Mapped Slave
through an AXI4 interconnect. Run time
interaction with this core requires the use of the
Vivado logic analyzer feature.
Features
• Provides AXI4 master interface
•Option to set AXI4 and AXI4-Lite interfaces
• User Selectable AXI data width – 32 and 64
• User Selectable AXI ID width up to four bits
• User Selectable AXI address width – 32 and
64
• Vivado logic analyzer Tcl Console interface
to interact with hardware
• Supports AXI4 and AXI4-Lite transactions
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
UltraScale+™, UltraScale™
Zynq
®
-7000 SoC
7 Series
Supported User
Interfaces
AXI4, AXI4-Lite
Resources Performance and Resource Utilization web page.
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Not Provided
Constraints File XDC
Simulation
Model
Not Provided
Supported
S/W Driver
N/A
Tested Design Flows
(2)
Design Entry Vivado
®
Design Suite
Simulation Not Supported
Synthesis
(3)
Vivado Synthesis
Support
All Vivado IP
Change Logs
Master Vivado IP Change Logs 72775
Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
IP catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
3. The standard synthesis flow for Synplify is not supported
for the core.
Send Feedback
JTAG to AXI Master v1.2 5
PG174 February 4, 2021 www.xilinx.com
Chapter 1
Overview
The JTAG to AXI Master is a customizable IP core which works as an AXI Master to drive AXI
transactions. This IP can be used in Vivado
®
IP integrator or can be instantiated in HDL in a
Vivado project.
Figure 1-1 shows an AXI system which uses the JTAG to AXI Master core as an AXI Master.
The JTAG to AXI Master core does not have its own address space and responds to all the
addresses you initiate. The JTAG to AXI Master core can communicate to all the downstream
slaves (S0, S1, and S2 in this case) and can coexist with the other AXI Master in the system.
Feature Summary
• Parametrized protocol choice:
°
AXI4
°
AXI4-Lite
• Parametrized Address width of 32 and 64
X-Ref Target - Figure 1-1
Figure 1-1: JTAG to AXI Master System
AXI Master
(Master 0)
JTAG to AXI
(Master 1)
AXI Master
(Master 2)
AXI Slave
(Slave 0)
AXI Slave
(Slave 1)
AXI Slave
(Slave 2)
AXI Interconnect
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