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三星闪存芯片,详细描述闪存的工作原理,有兴趣的网友可以看看,呵呵
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FLASH MEMORY
1
K9F5608D0C
K9F5608Q0C
K9F5608U0C
K9F5616D0C
K9F5616Q0C
K9F5616U0C
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
1.0
2.0
2.1
2.2
2.3
2.4
2.5
Remark
Advance
Preliminary
Preliminary
Preliminary
History
Initial issue.
1.Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 37)
4. Add the specification of Block Lock scheme.(Page 32~35)
5. Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
6. Pin assignment of WSOP #38 pin is changed.
(before) LOCKPRE --> (after) N.C
1. The Maximum operating current is changed.
Program : Icc2 20mA-->25mA
Erase : Icc3 20mA-->25mA
The min. Vcc value 1.8V devices is changed.
K9F56XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9F5608U0C-FCB0,FIB0
K9F5608Q0C-HCB0,HIB0
K9F5616U0C-HCB0,HIB0
K9F5616U0C-PCB0,PIB0
K9F5616Q0C-HCB0,HIB0
K9F5608U0C-HCB0,HIB0
K9F5608U0C-PCB0,PIB0
Errata is added.(Front Page)-K9F56XXQ0C
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification 45 15 25 50 15 25 30 45
Relaxed value 60 20 40 60 20 40 40 55
New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
1. The guidence of LOCKPRE pin usage is changed.
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-
READ, connect it Vss.(Before)
--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect
it Vss or leave it N.C(After)
2. 2.65V device is added.
3.Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Draft Date
Apr. 25th 2002
Dec.14th 2002
Jan. 17th 2003
Mar. 5th 2003
Mar. 13rd 2003
Mar. 26th 2003
Apr. 4th 2003
Jun. 30th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
FLASH MEMORY
2
K9F5608D0C
K9F5608Q0C
K9F5608U0C
K9F5616D0C
K9F5616Q0C
K9F5616U0C
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
2.6
2.7
2.8
2.9
3.0
RemarkHistory
1. tREA value of 1.8V device is changed.
K9F56XXQ0C : tREA 30ns --> 35ns
2. Errata is deleted.
1. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
K9F56XXU0C
K9F56XXD0C 50 15 25 50 15 25 30 45
K9F56XXQ0C 60 20 40 60 20 40 40 55
1. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
K9F5608Q0C 50 15 25 50 15 25 35 45
K9F5616Q0C 60 20 40 60 20 40 40 55
1. The Test Condition for Stand-by Currents are changed.
ISB1: CE=VIH, WP=0V/VCC -->> CE=VIH, WP=LOCKPRE=0V/VCC
ISB2: CE=VCC-0.2, WP=0V/VCC -->> CE=VCC-0.2, WP=LOCKPRE=0V/VCC
2. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
1. PKG(TSOP1, WSOP1) Dimension Change
Draft Date
Aug. 18th 2003
Oct. 28th 2003
Dec. 17th 2003
Apr. 24th 2004
May. 24th 2004
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
FLASH MEMORY
3
K9F5608D0C
K9F5608Q0C
K9F5608U0C
K9F5616D0C
K9F5616Q0C
K9F5616U0C
GENERAL DESCRIPTION
FEATURES
• Voltage Supply
- 1.8V device(K9F56XXQ0C) : 1.70~1.95V
- 2.65V device(K9F56XXD0C) : 2.4~2.9V
- 3.3V device(K9F56XXU0C) : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array
- X8 device(K9F5608X0C) : (32M + 1024K)bit x 8 bit
- X16 device(K9F5616X0C) : (16M + 512K)bit x 16bit
- Data Register
- X8 device(K9F5608X0C) : (512 + 16)bit x 8bit
- X16 device(K9F5616X0C) : (256 + 8)bit x16bit
• Automatic Program and Erase
- Page Program
- X8 device(K9F5608X0C) : (512 + 16)Byte
- X16 device(K9F5616X0C) : (256 + 8)Word
- Block Erase :
- X8 device(K9F5608X0C) : (16K + 512)Byte
- X16 device(K9F5616X0C) : ( 8K + 256)Word
• Page Read Operation
- Page Size
- X8 device(K9F5608X0C) : (512 + 16)Byte
- X16 device(K9F5616X0C) : (256 + 8)Word
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)*
*K9F5616Q0C : 60ns
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
• Power-On Auto-Read Operation
• Safe Lock Mechanism
• Package
- K9F56XXX0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F56XXX0C-DCB0/DIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- K9F5608U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F56XXX0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F56XXX0C-HCB0/HIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- K9F5608U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F5608U0C-V,F(WSOPI ) is the same device as
K9F5608U0C-Y,P(TSOP1) except package type.
Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0C is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V,
3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can
be performed in typical 200µs on a 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(K9F5616Q0C : 60ns)
cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write
control automates all program and erase functions including pulse repetition, where required, and internal verification and margining
of data. Even the write-intensive systems can take advantage of the K9F56XXX0C′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F56XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization PKG Type
K9F5608Q0C-D,H
1.70 ~ 1.95V
X8
TBGA
K9F5616Q0C-D,H X16
K9F5608D0C-Y,P
2.4 ~ 2.9V
X8
TSOP1
K9F5608D0C-D,H TBGA
K9F5616D0C-Y,P
X16
TSOP1
K9F5616D0C-D,H TBGA
K9F5608U0C-Y,P
2.7 ~ 3.6V
X8
TSOP1
K9F5608U0C-D,H TBGA
K9F5608U0C-V,F WSOP1
K9F5616U0C-Y,P
X16
TSOP1
K9F5616U0C-D,H TBGA
FLASH MEMORY
4
K9F5608D0C
K9F5608Q0C
K9F5608U0C
K9F5616D0C
K9F5616Q0C
K9F5616U0C
PIN CONFIGURATION (TSOP1)
K9F56XXU0C-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
LOCKPRE
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
LOCKPRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X8X16 X16X8
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.16
+0.07
-0.03
0.008
+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40
MAX
12.00
0.472
0.10
0.004
MAX
0.25
0.010
( )
0.039±0.002
1.00±0.05
0.002
0.05
MIN
0.047
1.20
MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8°
0.010
0.25
TYP
0.125
+0.075
0.035
0.005
+0.003
-0.001
0.50
0.020
( )
0.20
+0.07
-0.03
FLASH MEMORY
5
K9F5608D0C
K9F5608Q0C
K9F5608U0C
K9F5616D0C
K9F5616Q0C
K9F5616U0C
63-Ball TBGA (measured in millimeters)
PACKAGE DIMENSIONS
9.00±0.10
#A1
Side View
Top View
0.90±0.10
0.45±0.05
4 3 2 1
A
B
C
D
G
Bottom View
11.00±0.10
63-∅0.45±0.05
0.80 x7= 5.60
11.00±0.10
0.80 x 5= 4.00
0.80
0.32±0.05
0.08MAX
B
A
2.80
2.00
9.00±0.10
(Datum B)
(Datum A)
0.20 M A B
∅
0.80
0.80 x11= 8.80
0.80 x 9= 7.20
6 5
9.00±0.10
E
F
H
K9F56XXX0C-DCB0,HCB0/DIB0,HIB0
R/B/WE/CEVssALE/WP
/RE CLE
NCNC
NC NC
Vcc
NCNC I/O0
I/O1NC NC VccQ I/O5 I/O7
VssI/O6I/O4I/O3I/O2Vss
NC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC NC
NC
NC
LOCKPRE
NC
NC
N.C
N.C N.C
N.C
N.C N.C
N.C
N.C
N.C N.C
N.CN.C
N.C N.C
N.C
N.C
N.C N.C
N.C
N.C N.C
N.C
N.C
N.C N.C
N.CN.C
N.C N.C
N.C
R/B/WE/CEVssALE/WP
/RE CLE
I/O7I/O5
I/O12 IO14
Vcc
I/O10I/O8 I/O1
I/O9I/O0 I/O3 VccQ I/O6 I/O15
VssI/O13I/O4I/O11I/O2Vss
NC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC NC
NC
NC
LOCKPRE
NC
NC
X16
X8
3 4 5 6 1 2
A
B
C
D
G
E
F
H
3 4 5 6 1 2
A
B
C
D
G
E
F
H
Top View
Top View
PIN CONFIGURATION (TBGA)
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