LCD5110+LPC824+menu单片机菜单系统

/**************************************************************************//** * @file system_LPC8xx.c * @brief CMSIS Device System Source File for * NXP LPC81x Device Series * @version V1.10 * @date 19. August 2014 * * @note * Copyright (C) 2014 ARM Limited. All rights reserved. * * @par * ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include <stdint.h> #include "LPC8xx.h" /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*- SystemCoreClock Configuration -------------------------------------------*/ // <e0> SystemCoreClock Configuration #define CLOCK_SETUP 1 // // <h> System Oscillator Control (SYSOSCCTRL) // <o.0> BYPASS: System Oscillator Bypass Enable // <i> If enabled then PLL input (sys_osc_clk) is fed // <i> directly from XTALIN and XTALOUT pins. // <o.1> FREQRANGE: System Oscillator Frequency Range // <i> Determines frequency range for Low-power oscillator. // <0=> 1 - 20 MHz // <1=> 15 - 25 MHz // </h> #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000 // // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL) // <0=> IRC Oscillator // <1=> Crystal Oscillator (SYSOSC) // <3=> CLKIN pin #define SYSPLLCLKSEL_Val 0x00000000 // Reset value: 0x000 // // <e> Clock Configuration (Manual) #define CLOCK_SETUP_REG 1 // // <h> WDT Oscillator Setting (WDTOSCCTRL) // <o.0..4> DIVSEL: Select Divider for Fclkana // <i> wdt_osc_clk = Fclkana / (2 � (1 + DIVSEL)) // <0-31> // <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana) // <1=> 0.6 MHz // <2=> 1.05 MHz // <3=> 1.4 MHz // <4=> 1.75 MHz // <5=> 2.1 MHz // <6=> 2.4 MHz // <7=> 2.7 MHz // <8=> 3.0 MHz // <9=> 3.25 MHz // <10=> 3.5 MHz // <11=> 3.75 MHz // <12=> 4.0 MHz // <13=> 4.2 MHz // <14=> 4.4 MHz // <15=> 4.6 MHz // </h> #define WDTOSCCTRL_Val 0x00000180 // Reset value: 0x0A0 // // <h> System PLL Setting (SYSPLLCTRL) // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) // <i> F_clkin must be in the range of 10 MHz to 25 MHz // <i> F_CCO must be in the range of 156 MHz to 320 MHz // <o.0..4> MSEL: Feedback Divider Selection // <i> M = MSEL + 1 // <0-31> // <o.5..6> PSEL: Post Divider Selection // <i> Post divider ratio P. Division ratio is 2 * P // <0=> P = 1 // <1=> P = 2 // <2=> P = 4 // <3=> P = 8 // </h> //#define SYSPLLCTRL_Val 0x00000041 // For 24 MHz // Reset value: 0x000 #define SYSPLLCTRL_Val 0x00000024 // For 30 Mhz // Reset value: 0x000 // // <o.0..1> Main Clock Source Select (MAINCLKSEL) // <0=> IRC Oscillator // <1=> PLL Input // <2=> WD Oscillator // <3=> PLL Output #define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000 // // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV) // <i> Divides main clock to provide system clock to core, memories, and peripherals. // <i> 0 = is disabled // <0-255> //#define SYSAHBCLKDIV_Val 0x00000001 // For 24 MHz // Reset value: 0x001 #define SYSAHBCLKDIV_Val 0x00000002 // For 30 MHz // Reset value: 0x001 // </e> // // <e> Clock Configuration (via ROM PLL API) #define CLOCK_SETUP_API 0 // // <o> PLL API Mode Select // <0=> Exact // <1=> Less than or equal // <2=> Greater than or equal // <3=> As close as possible #define PLL_API_MODE_Val 3 // // <o> CPU Frequency [Hz] <1000000-30000000:1000> #define PLL_API_FREQ_Val 30000000 // </e> // // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000> // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz // #define XTAL_CLK_Val 12000000ul /* //-------- <<< end of configuration section >>> ------------------------------ */ /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */ #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */ #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */ #define __CLKIN_CLK ( 12000000UL) /* CLKIN pin frequency */ /*---------------------------------------------------------------------------- Check the register settings *----------------------------------------------------------------------------*/ #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) #define CHECK_RSVD(val, mask) (val & mask) #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) #error "SYSOSCCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) #error "WDTOSCCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) #error "SYSPLLCLKSEL: Value out of range!" #endif #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F)) #error "SYSPLLCTRL: Invalid values of reserved bits!" #endif #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) #error "MAINCLKSEL: Invalid values of reserved bits!" #endif #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) #error "SYSAHBCLKDIV: Value out of range!" #endif #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API ) #error "You must select either manual or API based Clock Configuration!" #endif #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000)) #error "XTAL frequency is out of bounds" #endif #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3)) #error "PLL API Mode Select not valid" #endif #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 30000000)) #error "CPU Frequency (API mode) not valid" #endif /*---------------------------------------------------------------------------- Calculate system core clock *----------------------------------------------------------------------------*/ #if (CLOCK_SETUP) /* Clock Setup */ /* sys_pllclkin calculation */ #if ((SYSPLLCLKSEL_Val & 0x03) == 0) #define __SYS_PLLCLKIN (__IRC_OSC_CLK) #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) #define __SYS_PLLCLKIN (__SYS_OSC_CLK) #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) #define __SYS_PLLCLKIN (__CLKIN_CLK) #else #error "Oops" #endif #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) + 1) << 1) #if (__FREQSEL == 0) #error "WDTOSCCTRL.FREQSEL undefined!" #eli