/**
******************************************************************************
* @file stm32f10x_tim.c
* @author MCD Application Team
* @version V3.1.2
* @date 09/28/2009
* @brief This file provides all the TIM firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_tim.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup TIM
* @brief TIM driver modules
* @{
*/
/** @defgroup TIM_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Defines
* @{
*/
/* ---------------------- TIM registers bit mask ------------------------ */
#define CR1_CEN_Set ((uint16_t)0x0001)
#define CR1_CEN_Reset ((uint16_t)0x03FE)
#define CR1_UDIS_Set ((uint16_t)0x0002)
#define CR1_UDIS_Reset ((uint16_t)0x03FD)
#define CR1_URS_Set ((uint16_t)0x0004)
#define CR1_URS_Reset ((uint16_t)0x03FB)
#define CR1_OPM_Reset ((uint16_t)0x03F7)
#define CR1_CounterMode_Mask ((uint16_t)0x038F)
#define CR1_ARPE_Set ((uint16_t)0x0080)
#define CR1_ARPE_Reset ((uint16_t)0x037F)
#define CR1_CKD_Mask ((uint16_t)0x00FF)
#define CR2_CCPC_Set ((uint16_t)0x0001)
#define CR2_CCPC_Reset ((uint16_t)0xFFFE)
#define CR2_CCUS_Set ((uint16_t)0x0004)
#define CR2_CCUS_Reset ((uint16_t)0xFFFB)
#define CR2_CCDS_Set ((uint16_t)0x0008)
#define CR2_CCDS_Reset ((uint16_t)0xFFF7)
#define CR2_MMS_Mask ((uint16_t)0xFF8F)
#define CR2_TI1S_Set ((uint16_t)0x0080)
#define CR2_TI1S_Reset ((uint16_t)0xFF7F)
#define CR2_OIS1_Reset ((uint16_t)0x7EFF)
#define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
#define CR2_OIS2_Reset ((uint16_t)0x7BFF)
#define CR2_OIS2N_Reset ((uint16_t)0x77FF)
#define CR2_OIS3_Reset ((uint16_t)0x6FFF)
#define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
#define CR2_OIS4_Reset ((uint16_t)0x3FFF)
#define SMCR_SMS_Mask ((uint16_t)0xFFF8)
#define SMCR_ETR_Mask ((uint16_t)0x00FF)
#define SMCR_TS_Mask ((uint16_t)0xFF8F)
#define SMCR_MSM_Reset ((uint16_t)0xFF7F)
#define SMCR_ECE_Set ((uint16_t)0x4000)
#define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
#define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
#define CCMR_TI13Direct_Set ((uint16_t)0x0001)
#define CCMR_TI24Direct_Set ((uint16_t)0x0100)
#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
#define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
#define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
#define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
#define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
#define CCMR_Offset ((uint16_t)0x0018)
#define CCER_CCE_Set ((uint16_t)0x0001)
#define CCER_CCNE_Set ((uint16_t)0x0004)
#define CCER_CC1P_Reset ((uint16_t)0xFFFD)
#define CCER_CC2P_Reset ((uint16_t)0xFFDF)
#define CCER_CC3P_Reset ((uint16_t)0xFDFF)
#define CCER_CC4P_Reset ((uint16_t)0xDFFF)
#define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
#define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
#define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
#define CCER_CC1E_Set ((uint16_t)0x0001)
#define CCER_CC1E_Reset ((uint16_t)0xFFFE)
#define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
#define CCER_CC2E_Set ((uint16_t)0x0010)
#define CCER_CC2E_Reset ((uint16_t)0xFFEF)
#define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
#define CCER_CC3E_Set ((uint16_t)0x0100)
#define CCER_CC3E_Reset ((uint16_t)0xFEFF)
#define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
#define CCER_CC4E_Set ((uint16_t)0x1000)
#define CCER_CC4E_Reset ((uint16_t)0xEFFF)
#define BDTR_MOE_Set ((uint16_t)0x8000)
#define BDTR_MOE_Reset ((uint16_t)0x7FFF)
/**
* @}
*/
/** @defgroup TIM_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_FunctionPrototypes
* @{
*/
static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
uint16_t TIM_ICFilter);
/**
* @}
*/
/** @defgroup TIM_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Private_Functions
* @{
*/
/**
* @brief Deinitializes the TIMx peripheral registers to their default reset values.
* @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
* @retval None
*/
void TIM_DeInit(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
if (TIMx == TIM1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
}
else if (TIMx == TIM2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
}
else if (TIMx == TIM3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
}
else if (TIMx == TIM4)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
}
else if (TIMx == TIM5)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
}
else if (TIMx == TIM6)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
}
else if (TIMx == TIM7)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
}
else
{
if (TIMx == TIM8)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_T
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电机开发板资料 加减速+步进电机+直流电机+细分+stm32(STC10X-DCMEK电机开发套件下位机控制程序V2.1) (175个子文件)
MotorTest.axf 404KB
MotorTest.uvgui_ly.bak 70KB
MotorTest_uvopt.bak 20KB
MotorTest_Uv2.Bak 6KB
MotorTest.Uv2.bak 6KB
MotorTest_Opt.Bak 5KB
MotorTest.opt.bak 5KB
MotorTest_sct.Bak 479B
stm32f10x_tim.c 102KB
stm32f10x_rcc.c 48KB
stm32f10x_adc.c 46KB
main.c 39KB
stm32f10x_i2c.c 37KB
stm32f10x_fsmc.c 34KB
stm32f10x_usart.c 34KB
stm32f10x_can.c 31KB
system_stm32f10x.c 30KB
stm32f10x_spi.c 29KB
stm32f10x_sdio.c 28KB
stm32f10x_dma.c 27KB
stm32f10x_flash.c 26KB
stm32f10x_gpio.c 19KB
core_cm3.c 17KB
stm32f10x_dac.c 14KB
stm32f10x_pwr.c 9KB
stm32f10x_rtc.c 8KB
stm32f10x_bkp.c 8KB
misc.c 7KB
stm32f10x_exti.c 7KB
stm32f10x_wwdg.c 6KB
stm32f10x_iwdg.c 5KB
stm32f10x_dbgmcu.c 4KB
stm32f10x_crc.c 3KB
stm32f10x_it.c 3KB
stm32f10x_tim.crf 317KB
stm32f10x_can.crf 310KB
main.crf 310KB
stm32f10x_i2c.crf 309KB
stm32f10x_flash.crf 309KB
stm32f10x_sdio.crf 308KB
stm32f10x_rcc.crf 306KB
stm32f10x_adc.crf 303KB
stm32f10x_dac.crf 302KB
stm32f10x_fsmc.crf 302KB
stm32f10x_usart.crf 301KB
stm32f10x_it.crf 301KB
stm32f10x_spi.crf 300KB
stm32f10x_bkp.crf 300KB
stm32f10x_gpio.crf 300KB
stm32f10x_dma.crf 299KB
stm32f10x_pwr.crf 299KB
stm32f10x_rtc.crf 299KB
system_stm32f10x.crf 297KB
stm32f10x_wwdg.crf 297KB
stm32f10x_iwdg.crf 297KB
stm32f10x_exti.crf 297KB
stm32f10x_dbgmcu.crf 297KB
stm32f10x_crc.crf 296KB
misc.crf 296KB
core_cm3.crf 4KB
stm32f10x_dbgmcu.d 1KB
stm32f10x_usart.d 1KB
stm32f10x_flash.d 1KB
stm32f10x_exti.d 1KB
stm32f10x_gpio.d 1KB
stm32f10x_fsmc.d 1KB
stm32f10x_sdio.d 1KB
stm32f10x_iwdg.d 1KB
stm32f10x_wwdg.d 1KB
stm32f10x_it.d 1KB
stm32f10x_rtc.d 1KB
stm32f10x_dac.d 1KB
stm32f10x_can.d 1KB
stm32f10x_i2c.d 1KB
stm32f10x_spi.d 1KB
stm32f10x_crc.d 1KB
stm32f10x_pwr.d 1KB
stm32f10x_tim.d 1KB
stm32f10x_adc.d 1KB
stm32f10x_bkp.d 1KB
stm32f10x_rcc.d 1KB
stm32f10x_dma.d 1KB
system_stm32f10x.d 1KB
main.d 1KB
misc.d 1KB
core_cm3.d 113B
startup_stm32f10x_cl.d 74B
MotorTest_MotorTest.dep 35KB
MotorTest_Target 1.dep 76B
stm32f10x.h 579KB
core_cm3.h 45KB
stm32f10x_tim.h 44KB
stm32f10x_rcc.h 28KB
stm32f10x_fsmc.h 26KB
stm32f10x_sdio.h 21KB
stm32f10x_adc.h 21KB
stm32f10x_dma.h 20KB
stm32f10x_can.h 20KB
stm32f10x_flash.h 19KB
stm32f10x_spi.h 18KB
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