NORFLASH烧写指南_nor烧录资源-CSDN文库

共23个文件

h：4个

s：4个

c：4个

FLASH

3星 · 超过75%的资源需积分: 10 45 浏览量 2008-11-13 10:55:36 上传评论收藏 600KB RAR 举报

资源推荐

资源详情

资源评论

收起资源包目录

NOR-FLASH-PGM.rar （23个子文件）

NOR-FLASH-PGM

NOR FLASH 烧写指南.pdf 242KB

SST39VF160

Func.c 4KB

Def.s 141B

Main.c 349B

DRIVER_Data

ARM

ObjectCode

DRIVER.axf 8KB

TargetDataWindows.tdt 54KB

CWSettingsWindows.stg 4KB

Init.s 602B

DRIVER.mcp 101KB

Types.h 79B

Func.h 369B

HY29F040

Func.c 4KB

Def.s 141B

Main.c 347B

DRIVER_Data

ARM

ObjectCode

DRIVER.axf 8KB

TargetDataWindows.tdt 54KB

CWSettingsWindows.stg 4KB

Init.s 604B

DRIVER.mcp 98KB

Types.h 80B

Func.h 367B

SST39VF160.pdf 382KB

HY29F040.pdf 157KB

Data Sheet

S71145-03-000 3/03 399

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit (x16) Multi-Purpose Flash

SST39LF160 / SST39VF160

FEATURES:

• Organized as 1M x16

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF160

– 2.7-3.6V for SST39VF160

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 12 mA (typical)

– Standby Current: 4 µA (typical)

– Auto Low Power Mode: 4 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Fast Read Access Time

– 55 ns for SST39LF160

– 70 and 90 ns for SST39VF160

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Word-Program Time: 14 µs (typical)

– Chip Rewrite Time: 15 seconds (typical) for

SST39LF/VF160

• Automatic Write Timing

– Internal V

Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST39LF/VF160 devices are 1M x16 CMOS Multi-

Purpose Flash (MPF) manufactured with SST’s propri-

etary, high performance CMOS SuperFlash technology.

The split-gate cell design and thick-oxide tunneling injec-

tor attain better reliability and manufacturability compared

with alternate approaches. The SST39LF160 write (Pro-

gram or Erase) with a 3.0-3.6V power supply. The

SST39VF160 write (Program or Erase) with a 2.7-3.6V

power supply. These devices conform to JEDEC standard

pinouts for x16 memories.

Featuring high performance Word-Program, the

SST39LF/VF160 devices provide a typical Word-Program

time of 14 µsec. These devices use Toggle Bit or Data#

Polling to indicate the completion of Program operation.

To protect against inadvertent write, they have on-chip

hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum

of applications, these devices are offered with a guaran-

teed typical endurance of 10,000 cycles. Data retention is

rated at greater than 100 years.

The SST39LF/VF160 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during Erase and Program than

alternative flash technologies. The total energy consumed

is a function of the applied voltage, current, and time of

application. Since for any given voltage range, the Super-

Flash technology uses less current to program and has a

shorter erase time, the total energy consumed during any

Erase or Program operation is less than alternative flash

technologies. These devices also improve flexibility while

lowering the cost for program, data, and configuration

storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as

is necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

To meet high density, surface mount requirements, the

SST39LF/VF160 are offered in a 48-lead TSOP and a

48-ball TFBGA package. See Figures 1 and 2 for pin

assignments.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

SST39LF/VF1603.0 & 2.7V 16Mb (x16) MPF memories

Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

The SST39LF/VF160 also have the Auto Low Power

mode which puts the device in a near standby mode after

data has been accessed with a valid Read operation. This

reduces the I

active read current from typically 15 mA to

typically 4 µA. The Auto Low Power mode reduces the typi-

cal I

active read current to the range of 1 mA/MHz of

read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition

used to initiate another Read cycle, with no access time

penalty. Note that the device does not enter Auto Low

Power mode after power-up with CE# held steadily low until

the first address transition or CE# is driven high.

Read

The Read operation of the SST39LF/VF160 is controlled by

CE# and OE#, both have to be low for the system to obtain

data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high. Refer to

the Read cycle timing diagram for further details (Figure 3).

Word-Program Operation

The SST39LF/VF160 are programmed on a word-by-word

basis. Before programming, the sector where the word

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either CE# or WE#, whichever occurs last.

The data is latched on the rising edge of either CE# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 20

µs. See Figures 4 and 5 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 16 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during the internal Program opera-

tion are ignored.

Sector-/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39LF/VF160 offer both Sector-Erase

and Block-Erase modes. The sector architecture is based

on uniform sector size of 2 KWord. The Block-Erase mode

is based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing waveforms. Any commands issued during the Sector-

or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF/VF160 provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 8 for timing diagram,

and Figure 19 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF/VF160 provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ

) and Toggle Bit (DQ

). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

Data# Polling (DQ

)

When the SST39LF/VF160 are in the internal Program

operation, any attempt to read DQ

will produce the com-

plement of the true data. Once the Program operation is

completed, DQ

will produce true data. Note that even

though DQ

may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ

will produce a ‘0’. Once the

internal Erase operation is completed, DQ

will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 6 for

Data# Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ

will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ

bit will

stop toggling. The Toggle Bit is valid after the rising edge of

fourth WE# (or CE#) pulse for Program operation. For Sec-

tor-, Block- or Chip-Erase, the Toggle Bit is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 7 for

Toggle Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF/VF160 provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode:

Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF/VF160 provide the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table

4 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

device to Read mode within T

. The contents of DQ

can be V

or V

, but no other value, during any SDP

command sequence.

Common Flash Memory Interface (CFI)

The SST39LF/VF160 also contain the CFI information to

describe the characteristics of the device. In order to enter

the CFI Query mode, the system must load the three-byte

sequence, similar to the Software ID Entry command. The

last byte cycle of this command loads 98H (CFI Query

command) to address 5555H. Once the device enters the

CFI Query mode, the system can read CFI data at the

addresses given in Tables 5 through 7. The system must

write the CFI Exit command to return to Read mode from

the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as

the SST39LF/VF160 and manufacturer as SST. This mode

may be accessed by software operations. Users may use

the Software Product Identification operation to identify the

part (i.e., using the device ID) when using multiple manu-

facturers in the same socket. For details, see Table 4 for

software operation, Figure 11 for the Software ID Entry and

Read timing diagram, and Figure 18 for the Software ID

Entry command sequence flowchart.

TABLE 1: P

RODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39LF/VF160 0001H 2782H

T1.2 399

Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 13 for timing waveform, and Figure 18 for a

flowchart.

FIGURE 1: P

IN ASSIGNMENTS FOR 48-LEAD TSOP

Y-Decoder

I/O Buffers and Data Latches

399 ILL B1.1

Address Buffer & Latches

X-Decoder

- DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

A15

A14

A13

A12

A11

A10

A19

WE#

A18

A17

A16

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

399 ILL F01.2

Standard Pinout

Top View

Die Up

SST39LF160/SST39VF160

Data Sheet

16 Mbit Multi-Purpose Flash

SST39LF160 / SST39VF160

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

TABLE 2: P

IN DESCRIPTION

Symbol Pin Name Functions

-A

Address Inputs To provide memory addresses. During Sector-Erase A

-A

address lines will select the

sector. During Block-Erase, A

-A

address line will select the block.

-DQ

Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF160

2.7-3.6V for SST39VF160

Ground

NC No Connection Unconnected pins

T2.3 399

399 ILL F02a.0

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

DQ11

DQ9

OE#

DQ6

DQ4

DQ3

DQ1

A B C D E F G H

SST39LF/VF160

TOP VIEW (balls facing down)

评论收藏

内容反馈

liangweichao

2018-06-29

对norflash烧写有研究的人们适用

chowooooo

粉丝: 0
资源: 10

NOR FLASH烧写指南

最新资源

NOR FLASH烧写指南

烧写norflash和nandflash区别

DM648的S29GL256 flash烧写程序

NOR-FLASH烧写指南

NOR FLASH 烧写指南.pdf

NOR_FLASH_读写指南

NOR FLASH编程指南

mini2440 nor flash 烧写配置文件

Jlink 针对mini2440（S3C2440）norflash烧写的配置文件

FL2440 Nor Flash烧写方法

ADS下QQ2440 NOR FLASH烧写程序

stm32 jlink 烧写外部NOR FLASH配置文件

MDK下LPC1788烧写外部NOR FLASH初始化文件

NAND FLASH PMON烧写指南

图解Jlink-Flash烧写NorFlash.pdf

SST_Flash.rar_ nor flash_flash SST_flash 烧写_nor flash_sst flas

jtag烧写nor flash

j-flash烧写2440的nor flash

【bingo】Jlink对2440外部norflash的烧写

通过STM32CubeMX制作外部Flash的烧写驱动_外部Flash的烧写驱动_

JLink烧写NOR Flash

JLink实现对GT2440开发板上的外部Nor Flash的烧写

嵌入式家园 - JLink烧写Nand_Nor Flash步骤指南-V1.3

nandflash_test.rar_nandflash_nandflash vhdl_norflash_norflash vh

Xilinx FPGA multiboot加载

简历模板大全

STM32F407_ADC_DMA_FFT

【无水印】UFS3.1协议，文档编号：JESD200E

LT6911UXC_Datasheet_R1.2.pdf

最新资源