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M25P64 flash芯片datasheet,内涵flash芯片详细时序图
M25P64 Figure 10. Write Disable(WRDD) Instruction Sequence 15 Read Identification(RDID) 16 Table 5. Read Identification(RDID)Data-Out Sequence 16 Figure 11. Read Identification(RDID)Instruction Sequence and Data-Out Sequence Read status Register(RDSR)...…… 画画画 画丽面面画 Table 6. Status Register Format WiP bit 17 WEL bit 17 BP2, BP1BPo bits srWd bit 17 Figure 12. Read Status Register(RDSR )Instruction Sequence and Data-Out Sequence.... 17 Write Status Register ( WRSR 18 Table 7. Protection modes 18 Figure 13. Write Status Register(WRSR)Instruction Sequence 19 Read Data Bytes(READ). 20 Figure 14. Read Data Bytes(READ) Instruction Sequence and Data-Out Sequence Read Data Bytes at Higher Speed (FAST READ) 21 Figure 15. Read Data Bytes at Higher Speed(FAST_ READ)Instruction and Data-Out Sequence 21 Page Program(PP)∴∴,, ,22 Figure 16 Page Program(PP)Instruction Sequence 22 Sector Erase(sE) 23 Figure 17 Sector Erase(SE) Instruction Sequence 23 Bulk Erase(BE)........ ,,,,,,,,,,,,,,24 Figure 18.Bulk Erase( BE)Instruction Sequence 24 Read Electronic Signature(RES) 25 Figure 19. Read Electronic Signature(RES) Instruction Sequence and Data-Out Sequence POWER-UP AND POWER-DOWN ,,,26 Figure 20 Power-up Timing 26 Table 8. Power-Up Timing and VWI Threshold INITIAL DELIVERY STATE MAXIMUM RATING Table 9. Absolute Maximum Ratings 28 DC AND AC PARAMETERS Table 10. Operating Conditions Table 11. Ac measurement Conditions Figure 21.AC Measurement l/o Waveform Table 12 Capacitance. Table 13. DC Characteristics .::·::: Table 14 Ac characteristics 31 Figure 22. Serial Input Timing 32 Figure 23. Write Protect Setup and Hold timing during WrSR when SRWD=1 32 Figure 24. Hold Timing 3/38 M25P64 Figure 25Output Timing PACKAGE MECHANICAL 34 Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline....... 34 Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm Package Mechanical data 34 Figure 27So16 wide-16 lead Plastic Small Outline, 300 mils body width ,,35 Table 16. So16 wide-16 lead Plastic Small Outline, 300 mils body width 35 PART NUMBERING ·: 36 Table 17. Ordering Information Scheme 36 REVISION HISTORY ,,,37 Table 18. Document Revision History ...,37 4/38 M25P64 SUMMARY DESCRIPTION Figure 3. VDFPN Connections The M25P64 is a 64Mbit(8M x 8) Serial Flash Memory, with advanced write protection mecha- nisms, accessed by a high speed SPI-compatible The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction M25P64 The memory is organized as 128 sectors, each containing 256 pages. Each page is 256 bytes s可1 wide. Thus, the whole memory can be viewed as 8PVcC consisting of 32768 pages, or 8388608 bytes Q日2 7 P HOLD The whole memory can be erased using the Bulk W43 6FC Erase instruction, or a sector at a time, using the SS 94 5P D Sector erase instruction A|08595 Figure 2. Logic Diagram VcC Note: 1. There is an exposed die paddle on the underside of the MLP8 package. Th ulled, internally, to Vss, and D Q must not be allowed to be connected to any other voltage or signal line on the PCB 2. See PACKAGE MECHANICAL section for package di mensions, and how to identify pin-1 M25P64 Figure 4. sO Connections M25P64 HOLD日1 16日C vcc日215日D 3 14 A07485 DU 4 13日DU DU日5 2日DU DU 06 11 DU 0日Vss Table 1. Signal Names Serial clock D Serial Data Input Serial Data Output 2. See PACKAGE MECHANICAL section for package di- mensions, and haw to identify pin -1 Chip select Write protect HOLD Hold Supply voltage Ground 5/38 M25P64 SIGNAL DESCRIPTION Serial Data Output(Q). This output signal is progress, the device will be in the Standby Power used to transfer data serially out of the device. mode Driving Chip Select(S)Low selects the de Data is shifted out on the falling edge of Serial vice, placing it in the Active Power mode Clock(C) After Power-up, a falling edge on Chip Select (s) Serial Data Input(D). This input signal is used to is required prior to the start of any instruction transter data serially into the device. It receives in- Hold(HOLD). The Hold(HOLD)signal is used to pause any serial communications with the device grammed Values are latched on the rising edge ot without deselecting the device Serial Clock(C) During the Hold condition, the Serial Data Output Serial Clock(C). This input signal provides the and Serial Clock(C)are Don' t Care ata Input (D) (Q)is high impedance, and Serial D timing of the serial interface. Instructions, address- es, or data present at Serial Data Input(D)are To start the hold condition the device must be se latched on the rising edge of Serial Clock( C).Data lected, with Chip select(s)driven LOW on Serial Data Output(Q)changes after the falling edge of Serial Clock(C) Write Protect (W). The main purpose of this in- put signal is to freeze the size of the area of mem- Chip Select(S). When this input signal is High ory that is protected against program or erase the device is deselected and Serial Data Output instructions (as specified by the values in the BP2, (Q)is at high impedance Unless an internal pro BP 1 and BPo bits of the Status Register) gram, Erase or Write Status Register cycle is in 6/38 M25P64 SPI MODES These devices can be driven by a microcontroller is available from the falling edge of Serial Clock with its SPl peripheral running in either of the two C) following modes: The difference between the two modes as shown CPOL=0, CPHA=O Figure 6., is the clock polarity when the bus CPOL=1. CPHA=1 master is in Stand-by mode and not transferring For these two modes, input data is latched in on data the rising edge of Serial Clock( C), and output data C remains at 0 for(CPOL=0, CPHA=O) C remains at 1 for(CPOL=1, CPHA=1) Figure 5. Bus Master and Memory Devices on the SPI Bus SPI Interface with (CPOL, CPHA) (0,0)or(1,1) SCK Bus Maste (ST6, ST7, ST9 ST10, Others) iory Device Devic HOLD Note: The Write Protect(W)and Hold(HOLD)signals should be driven, High or Low as appropriate Figure 6. SPl Modes Supported D MSB 01438B 7/38 M25P64 OPERATING FEATURES Page Programming Active Power and Standby Power Modes To program one data byte, two instructions are re- When Chip Select (S)is Low, the device is select- quired: Write Enable(WREN), which is one byte, ed, and in the Active Power mode and a Page Program(PP) sequence, which con sists of four bytes plus data. This is followed by the When Chip Select(S)is High, the device is dese lected but could remain in the active power mode internal Program cycle(of duration tpp) until all internal cycles have completed(Program To spread this overhead, the Page Program(PP) Erase, Write Status Register). The device then nstruction allows up to 256 bytes to be pro goes in to the Standby Power mode. The device grammed at a time(changing bits from 1 to 0), pro- consumption drops to Icc1 vided that they lie in consecutive addresses on the same page oT memory Status Register Sector erase and bulk erase The Status Register contains a number of status and control bits that can be read or set(as appro The Page Program(PP)instruction allows bits to priate)by specific instructions be reset from 1 to O. Before this can be applied, the bytes of memory need to have been erased to all WIP bit. The Write In Progress(WIP)bit indicates Is(FFh). This can be achieved either a sector at a whether the memory is busy with a Write Status time, using the Sector Erase(SE)instruction, or Register, Program or Erase cycle throughout the entire memory, using the Bulk Erase(BE)instruction. This starts an internal WEL bit. The Write Enable Latch(WEL) bit indi- Erase cycle(of duration tsE or tBE cates the status of the internal write enable latch The Erase instruction must be preceded by a Write Enable(WREn)instruction BP2, BP1, BPD bits. The Block Protect (BP2, BP1, BPo)bits are non-volatile. They define the Polling During a Write, Program or Erase Cycle size of the area to be software protected against Program and Erase instructions A further improvement in the time to Write status Register(WRSR), Program(PP)or Erase(sE or SRWD bit. The Status Register Write Disable BE)can be achieved by not waiting for the worst (SRWD) bit is operated in conjunction with the case delay(tW, tpP, tsE, or tBE). The Write In Write Protect (W)signal. The Status Register Progress(WiP)bit is provided in the Status Regis Write Disable (SRWD)bit and Write protect (W ter so that the application program can monitor its signal allow the device to be put in the Hardware value, polling it to establish when the previous Protected mode, In this mode the non-volatile bits Write cycle, Program cycle or Erase cycle is com of the Status Register(SRWD, BP2, BP1, BPO) plete become read-only bits 8/38 M25P64 Protection modes Power-up The environments where non-volatile memory de Write Disable(WRDI)instruction vices are used can be very noisy. No sPI device completion can operate correctly in the presence of excessive Write Status Register(WRSR)instruction noise. To help combat this, the M25P64 features completion the following data protection mechanisms Page Program(PP)instruction completion Power On Reset and an internal timer(tpu) Sector Erase(SE)instruction completion can provide protection against inadvertant changes while the power supply is outside the Bulk Erase(BE)instruction completion operating specification The Block Protect(BP2, BP1, BPo)bits allow Program, Erase and Write Status Register part of the memory to be configured as read- instructions are checked that they consist of a only. This is the Software Protected Mode number of clock pulses that is a multiple of (SPM) eight, before they are accepted for execution The Write Protect (W)signal allows the Block All instructions that modify data must be Protect(BP2, BP1, BP0) bits and Status preceded by a Write Enable(WREN Register Write Disable(SRWD) bit to be instruction to set the write enable latch protected. This is the Hardware Protected (WEL bit. This bit is returned to its reset state Mode (HPm) by the following events Table 2. protected area sizes Status Register Content Memory Content BP2BP1BPO Bit Bit Protected area Bit Unprotected Area 0 onone All sectors(128 sectors: 0 to 127) 0000 0 1 Upper 64th(2 sectors: 126 and 127) Lower 63/64ths(126 sectors: 0 to 125) o Upper 32nd (4 sectors: 124 to 127) 110 Lower 31/32nds(124 sectors: 0 to 123) 1 Upper sixteenth(8 sectors: 120 to 127)Lower 15/16ths(120 sectors: 0 to 119) o Upper eighth(16 sectors: 112 to 127) Lower seven-eighths(112 sectors: 0 to 111) 1111 1 Upper quarter(32 sectors: 96 to 127) Lower three-quarters(96 sectors: 0 to 95) 0 Upper half(64 sectors: 64 to 127) Lower half(64 sectors: 0 to 63) 1 All sectors(128 sectors: 0 to 127) none Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect(BP2, BP1, BPO)are 0 9/38 M25P64 Hold Condition rising edge does not coincide with Serial Clock(C The Hold(HOLD) signal is used to pause any se- being Low, the Hold condition ends after Serial rial communications with the device without reset- Clock(C)next goes Low. (This is shown in Figure 7) signal Low does not terminate any Write Status During the Hold condition, the serial data output Register, Program or Erase cycle that is currently In progress and Serial Clock(C)are Dont Care To enter the hold condition the device must be Normally, the device is kept selected, with Chip selected, with Chip Select (S)Low Select (s)driven Low, for the whole duration of the The hold condition starts on the falling edge of the Hold condition this is to ensure that the state of the internal logic remains unchanged from the mo- Hold(HOLD) signal, provided that this coincides with Serial Clock(C) being Low(as shown in Fig ment of entering the hold condition ure 7.) If Chip Select (s)goes High while the device is in The Hold condition ends on the rising edge of the the Hold condition, this has the effect of resetting the internal logic of the device. To restart commu- Hold(HOLD)signal, provided that this coincides with Serial Clock(C)being Low nication with the device, it is necessary to drive Hold(HoLD) High, and then to drive Chip select If the falling edge does not coincide with Serial (S)Low. This prevents the device from going back Clock(C)being Low, the hold condition starts af- to the Hold condition ter Serial Clock(C)next goes Low. Similarly, if the Fiqure 7. Hold Condition Activation c凵「「L「凵「「「凵「L「L Hold (standard use) (non-standard use) A|02029D 1038

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