vhdl语言编写的小程序2*2乘法器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY NPMULT IS

PORT ( 

   MCLK : IN STD_LOGIC;

   A, B : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

   R : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
   c: out STD_LOGIC_VECTOR(3 downto 0)

);

END NPMULT;

 

ARCHITECTURE A1 OF NPMULT IS

SIGNAL AA, AB, AS, BS : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0) ;