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specification

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PCI Express

™

Base Specification

Revision 1.1

March 28, 2005

PCI EXPRESS BASE SPECIFICATION, REV 1.1

Contents

OBJECTIVE OF THE SPECIFICATION.................................................................................... 19

DOCUMENT ORGANIZATION ................................................................................................ 19

DOCUMENTATION CONVENTIONS ...................................................................................... 20

TERMS AND ACRONYMS........................................................................................................ 21

REFERENCE DOCUMENTS...................................................................................................... 26

1. INTRODUCTION ................................................................................................................ 27

1.1. A T

HIRD GENERATION I/O INTERCONNECT ................................................................... 27

1.2. PCI EXPRESS LINK ........................................................................................................ 29

1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 30

1.3.1. Root Complex........................................................................................................ 30

1.3.2. Endpoints .............................................................................................................. 31

1.3.3. Switch.................................................................................................................... 34

1.3.4. Root Complex Event Collector.............................................................................. 35

1.3.5. PCI Express-PCI Bridge....................................................................................... 35

1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 35

1.5. PCI EXPRESS LAYERING OVERVIEW ............................................................................. 36

1.5.1. Transaction Layer................................................................................................. 37

1.5.2. Data Link Layer .................................................................................................... 37

1.5.3. Physical Layer ...................................................................................................... 38

1.5.4. Layer Functions and Services............................................................................... 38

2. TRANSACTION LAYER SPECIFICATION ..................................................................... 43

2.1. T

RANSACTION LAYER OVERVIEW.................................................................................. 43

2.1.1. Address Spaces, Transaction Types, and Usage................................................... 44

2.1.2. Packet Format Overview ...................................................................................... 46

2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 47

2.2.1. Common Packet Header Fields ............................................................................ 47

2.2.2. TLPs with Data Payloads - Rules ......................................................................... 50

2.2.3. TLP Digest Rules .................................................................................................. 52

2.2.4. Routing and Addressing Rules.............................................................................. 52

2.2.5. First/Last DW Byte Enables Rules........................................................................ 55

2.2.6. Transaction Descriptor......................................................................................... 57

2.2.7. Memory, I/O, and Configuration Request Rules................................................... 62

2.2.8. Message Request Rules......................................................................................... 65

2.2.9. Completion Rules.................................................................................................. 76

PCI EXPRESS BASE SPECIFICATION, REV 1.1

2.3. HANDLING OF RECEIVED TLPS...................................................................................... 78

2.3.1. Request Handling Rules........................................................................................ 81

2.3.2. Completion Handling Rules.................................................................................. 93

2.4. T

RANSACTION ORDERING .............................................................................................. 95

2.4.1. Transaction Ordering Rules ................................................................................. 95

2.4.2. Update Ordering and Granularity Observed by a Read Transaction .................. 99

2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 100

2.5. V

IRTUAL CHANNEL (VC) MECHANISM ....................................................................... 100

2.5.1. Virtual Channel Identification (VC ID) .............................................................. 103

2.5.2. TC to VC Mapping.............................................................................................. 103

2.5.3. VC and TC Rules................................................................................................. 105

2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 106

2.6.1. Flow Control Rules............................................................................................. 107

2.7. D

ATA INTEGRITY ......................................................................................................... 116

2.7.1. ECRC Rules ........................................................................................................ 117

2.7.2. Error Forwarding ............................................................................................... 121

2.8. C

OMPLETION TIMEOUT MECHANISM ........................................................................... 123

2.9. LINK STATUS DEPENDENCIES ...................................................................................... 124

2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 124

2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 125

3. DATA LINK LAYER SPECIFICATION.......................................................................... 127

3.1. DATA LINK LAYER OVERVIEW .................................................................................... 127

3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 129

3.2.1. Data Link Control and Management State Machine Rules ................................ 130

3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 132

3.3.1. Flow Control Initialization State Machine Rules ............................................... 132

3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 136

3.4.1. Data Link Layer Packet Rules ............................................................................ 136

3.5. DATA INTEGRITY ......................................................................................................... 141

3.5.1. Introduction......................................................................................................... 141

3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 141

3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 153

4. PHYSICAL LAYER SPECIFICATION ............................................................................ 161

4.1. I

NTRODUCTION ............................................................................................................ 161

4.2. LOGICAL SUB-BLOCK................................................................................................... 161

4.2.1. Symbol Encoding ................................................................................................ 162

4.2.2. Framing and Application of Symbols to Lanes................................................... 165

4.2.3. Data Scrambling ................................................................................................. 168

4.2.4. Link Initialization and Training.......................................................................... 169

4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 177

4.2.6. Link Training and Status State Rules.................................................................. 180

4.2.7. Clock Tolerance Compensation.......................................................................... 210

4.2.8. Compliance Pattern ............................................................................................ 211

PCI EXPRESS BASE SPECIFICATION, REV 1.1

4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 213

4.3.1. Electrical Sub-Block Requirements .................................................................... 213

4.3.2. Electrical Signal Specifications .......................................................................... 217

4.3.3. Differential Transmitter (TX) Output Specifications .......................................... 222

4.3.4. Differential Receiver (RX) Input Specifications ................................................. 228

5. POWER MANAGEMENT................................................................................................. 231

5.1. OVERVIEW ................................................................................................................... 231

5.1.1. Statement of Requirements.................................................................................. 232

5.2. L

INK STATE POWER MANAGEMENT............................................................................. 232

5.3. PCI-PM S

OFTWARE COMPATIBLE MECHANISMS ........................................................ 237

5.3.1. Device Power Management States (D-States) of a Function.............................. 237

5.3.2. PM Software Control of the Link Power Management State.............................. 241

5.3.3. Power Management Event Mechanisms ............................................................. 246

5.4. N

ATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 253

5.4.1. Active State Power Management (ASPM) .......................................................... 253

5.5. A

UXILIARY POWER SUPPORT ....................................................................................... 269

5.5.1. Auxiliary Power Enabling................................................................................... 269

5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 270

6. SYSTEM ARCHITECTURE ............................................................................................. 273

6.1. INTERRUPT AND PME SUPPORT................................................................................... 273

6.1.1. Rationale for PCI Express Interrupt Model........................................................ 273

6.1.2. PCI Compatible INTx Emulation........................................................................ 274

6.1.3. INTx Emulation Software Model ........................................................................ 274

6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 274

6.1.5. PME Support....................................................................................................... 276

6.1.6. Native PME Software Model .............................................................................. 276

6.1.7. Legacy PME Software Model ............................................................................. 277

6.1.8. Operating System Power Management Notification........................................... 277

6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 277

6.2. E

RROR SIGNALING AND LOGGING................................................................................ 278

6.2.1. Scope................................................................................................................... 278

6.2.2. Error Classification ............................................................................................ 278

6.2.3. Error Signaling ................................................................................................... 280

6.2.4. Error Logging ..................................................................................................... 287

6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 290

6.2.6. Error Message Controls ..................................................................................... 292

6.2.7. Error Listing and Rules ...................................................................................... 293

6.2.8. Virtual PCI Bridge Error Handling.................................................................... 297

6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 298

6.3.1. Introduction and Scope....................................................................................... 298

6.3.2. TC/VC Mapping and Example Usage................................................................. 299

6.3.3. VC Arbitration .................................................................................................... 301

6.3.4. Isochronous Support ........................................................................................... 309

6.4. DEVICE SYNCHRONIZATION......................................................................................... 312

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mydazzy

2014-01-25

PCIe 1.1比较合适学习PCIe规范，先把1.1的看明白，然后再看PCIe 2.1/3.0等规范
laihuachao

2016-09-05

分少，下下来了解下硬件规范
kaqi0001

2013-12-10

很不错，参考很有帮助
jeddy_ku

2015-08-04

不错，就是我要的1.1规范
my-blog

2013-05-22

不错的文档，参考了

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changying123

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