/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
* stm32f4xx_Clock_Configuration_V1.0.0.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F4xx device revision | Rev A
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 8000000
*-----------------------------------------------------------------------------
* PLL_M | 8
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | 192
*-----------------------------------------------------------------------------
* PLLI2S_R | 5
*-----------------------------------------------------------------------------
* I2S input clock(Hz) | 38400000
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* High Performance mode | Enabled
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | OFF
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 8
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
I2SCLK = PLLI2S_VCO / PLLI2S_R */
#define PLLI2S_N 192
#define PLLI2S_R 5
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreC
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nRF24L01.uvgui_Soe.bak 132KB
nRF24L01_uvproj.bak 19KB
nRF24L01_uvopt.bak 17KB
system_stm32f4xx.c 21KB
motor.c 8KB
stm32f4xx_it.c 6KB
uart.c 3KB
main.c 1KB
stm32f4xx_tim.crf 404KB
main.crf 397KB
stm32f4xx_rcc.crf 394KB
stm32f4xx_adc.crf 392KB
stm32f4xx_dma.crf 391KB
stm32f4xx_it.crf 391KB
uart.crf 390KB
stm32f4xx_usart.crf 390KB
stm32f4xx_flash.crf 390KB
stm32f4xx_spi.crf 389KB
stm32f4xx_sdio.crf 389KB
motor.crf 388KB
stm32f4xx_dac.crf 388KB
stm32f4xx_gpio.crf 387KB
system_stm32f4xx.crf 386KB
stm32f4xx_exti.crf 386KB
stm32f4xx_syscfg.crf 385KB
misc.crf 385KB
stm32f4xx_syscfg.d 3KB
stm32f4xx_flash.d 3KB
stm32f4xx_usart.d 3KB
stm32f4xx_sdio.d 3KB
stm32f4xx_exti.d 3KB
stm32f4xx_gpio.d 3KB
stm32f4xx_it.d 3KB
stm32f4xx_rcc.d 3KB
stm32f4xx_tim.d 3KB
stm32f4xx_dma.d 3KB
stm32f4xx_dac.d 3KB
stm32f4xx_adc.d 3KB
stm32f4xx_spi.d 3KB
system_stm32f4xx.d 3KB
main.d 3KB
misc.d 2KB
uart.d 2KB
motor.d 2KB
startup_stm32f4xx.d 100B
nRF24L01_Target 1.dep 10KB
stm32f4xx_conf.h 4KB
stm32f4xx_it.h 2KB
main.h 908B
uart.h 581B
my_type.h 292B
motor.h 179B
Motor.htm 69KB
ExtDll.iex 19B
Motor.lnp 566B
nRF24L01.lnp 512B
startup_stm32f4xx.lst 88KB
Motor.map 104KB
nRF24L01.map 25KB
stm32f4xx_tim.o 551KB
stm32f4xx_rcc.o 482KB
stm32f4xx_adc.o 474KB
stm32f4xx_flash.o 461KB
stm32f4xx_usart.o 460KB
stm32f4xx_sdio.o 460KB
stm32f4xx_spi.o 454KB
stm32f4xx_dma.o 447KB
stm32f4xx_it.o 443KB
stm32f4xx_dac.o 443KB
stm32f4xx_gpio.o 438KB
main.o 434KB
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misc.o 425KB
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