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Digital Integrated Circuit Design Using Verilog and Systemverilog 作者: Ronald W. Mehler; 语种: 英语(English) 出版日期: 2014-09-30 出版社: Newnes 页数: 448 简介:作者是加州大学北岭分校教授,在数字电路设计领域具有很深的造诣,这本教材是其学术集大成
About the author Ronald w. mehler Ronald Mehler is a professor of electrical and computer engineering at California State University, Northridge. Prior to joining the faculty of CSUN, he worked as an engineer for several companies, primarily designing digital-integrated circuits for aviation, telecommunications, and general-purpose computing applications He has been designing integrated circuits with hardware description languages since 1988 He holds a B.s. in electrical and computer engineering from the University of Wisconsin, an M.s. in electrical engineering from Texas a&M University, and a Ph. D. in electrical engineering from the University of Texas at Dallas Preface This is a book about using verilog and system verilog to design digital-integrated circuits. It takes the readers from the most fundamental elements of digital design through the design of sophisticated components and interfaces. Included are guide lines for optimizing designs and creating robust, reliable systems Digital-integrated circuits are the electronic brains behind all modern electronics Communications, computers, aviation, automobiles, consumer appliances, and much more: if it runs on electricity, it has digital-integrated circuits someplace in the background. All modern digital circuits are designed with a hardware descrip tion language, and Verilog/System Verilog is the engineer's choice for the majority of new designs Beyond simply a language reference manual, this book not only teaches the syntax of verilog/System Verilog hardware description language, it teaches how to effec tively use it to produce optimized circuits that will work the first time, every time It contains little-understood information on asynchronous interfaces. a common source of failure in digital designs, and a guide to design partitioning to produce optimal designs While no prior exposure to any hardware description language is expected, readers should have some basic knowledge of Boolean algebra and electrical engineering fundamentals such as Ohm's law This book is based on courses taught by the author at California State University The courses are themselves based on the authors 20 years of experience in private industry designing digital circuits prior to joining the CsU faculty XII Acknowledgments The author would first and foremost like to thank janice mehler for finding and correcting innumerable errors and instances of generally poor writing without her editing efforts, this would be a much worse book Thanks are also due to Troy Wood at Synopsys, Inc, who provided wise sug gestions and shepherded relevant passages through legal wickets and to Texas Instruments for allowing use of circuit images All trademarks and copyrights used herein are the property of their respective owners XV Chapter Introduction OUTLINE Who should read this book 1 Hardware description languages and methodology 2 What this book covers 3 Historical perspective 4 Verilog and System Verilog 7 Book organization 7 Modern digital circuits are designed at an abstract level using a hardware descript tion language and logic synthesis. This book covers the use of the most popular such language, Verilog/ System Verilog. The rest of this chapter presents some historical context for designing with verilog and offers a brief overview in each chapter WHO SHOULD READ THIS BOOK This book is intended for those who design, verify, or otherwi work with digital circuitry. It is expected that readers will have some familiarity with digital concepts such as Boolean logic and flipflops but no prior exposure to Verilog or any other hardware description language(HDL) is needed. A review of the funda mental digital concepts is included in Appendix b Verilog and System Verilog are equally useful for the design of field programmable gate arrays(FPGAs)and custom hardware devices. The techniques for designing both are covered in this book When used as a textbook. it is suitable for advanced undergradu ate and beginning graduate courses in digital design Digital Integrated Circuit Design Using Verilog and System Verilog 978-0-12-408059-1 Copyright O 2015 Ronald w. Mehler. Published by Elsevier. Inc. All rights reserved 2 CHAPTER 1 Introduction HARDWARE DESCRIPTION LANGUAGES AND METHODOLOGY Verilog is an HDL. System verilog is a superset of verilog that also includes numerous constructs that are useful for verifying de- signs but do not always have any meaning for circuit description System verilog is sometimes called a hardware design and verifi- cation language(HDVL) or just a hardware verification language (HVL rather than an hDL HDLS provide a method of specifying the behavior of a design without specifying any implementation. They use programmin language-like syntax to indicate the logical functions that are to be implemented A page of Verilog hardware description can look a lot like a page of a C language computer program, as their syntaxes are similar, but their objectives are different. A computer program is a series of instructions that can be run on a suitable computer An HDL specification of a design describes the functioning of a design that can be turned into a new machine The former utilizes existing hardware to transform data The latter is used to create new hardware. HDL design is not computer programming USing an HDL, a proposed new design can be encoded and the design verified before any hardware is constructed USing an HDL llows designers to operate at a higher level of abstraction than previous design methodologies, providing a huge boost in effi and productivity. Once an hdl design has been verified the code can be turned from an abstract, technology-independent description into a technology specific gate-level implementation. This transformation is accom plished through a highly automated process of logic synthesis Several design automation companies make logic synthesizers that can be used to affect this step. Postsynthesis, there are several more steps that must be taken before the design will be ready for production Figure 1. I shows a typical HDL design flow. A concept for a new design is, if economics warrant, turned into a design specifica tion. Design engineers take this specification and turn it into an What this book covers 3 Design Specification HDL Codins g Simulation HDI Vectors Simulation Simulation Passed? ogIc Synthe FIGURE 1. 1 HDL design flow HDL description. In parallel, verification engineers write tests to determine if the HDL design implementation is correct, meets all the design specifications, and is sufficiently robust to operate under a variety of error conditions. Code written by the design team and the verification team is simulated. Once all agree that the hdl circuit description is complete and correct, the design is synthesized and turned into a gate-level netlist referencing a specific semiconductor technology WHAT THIS BOOK COVERS This is a book about designing digital circuits with Verilog and System Verilog. It assumes no prior knowledge of verilog or any HDL. It covers language syntax and best practices for producin reliable digital-integrated circuits It includes hundreds of exam- oles showing how the various constructs are used to effectively create hardware designs. It also includes numerous examples of 4 CHAPTER 1 Introduction test fixtures to verify the correct functioning of the provided de sign examples This book takes the reader from a design specification through a verified design ready for synthesis Covered are all parts of Verilog and System Verilog that are useful for circuit design as well as some components of the languages that are needed for verification but are not meaningful for circuit description System Verilog is an all-encompassing language that can be used for a variety of verification and even unrelated programming tasks that are not fundamental to hardware design. Constructs that are not directly related to hardware design are not covered HISTORICAL PERSPECTIVE The earliest integrated circuits were designed at the subtransistor level. Individually crafting each transistor, a team of four engi neers took 4 months to complete the first microprocessor. That processor, the four-bit Intel 4004, used 2300 transistors. It went Into production in 1971 As this book is being written, some state of the art processors have upwards of three billion transistors. If engineers still work at the same rate of transistor design. a team of four would take nearly half a million years to turn out a new processor The density of transistors that could be formed on a single die increased exponentially over the past four decades as semicon- ductor manufacturing prowess improved. with the increase in transistor density, crafting each transistor individually became an untenable methodology. The necessity of developing ever-larger circuits led to the creation of more abstract models of combina tional and sequential functions that could be reused in schematic representations of new circuits Designing at the gate level rather than at the transistor level and increasing the size of the design teams were the next steps in Historical perspective 5 design methodology and management. These moves decreased the time to complete designs by orders of magnitude, but the inex rable increase in semiconductor density opened the doors to newer design methodologies. Unlike transistor density, design team size could not increase exponentially, year after year, for decades Verifying the behavior of these ever more complex circuit designs before committing to building the first prototype was another challenge. Simulations of the logical behavior of an abstract de sign became standard operating procedure, yet as design com plexity continued to accelerate, determining if designs were logi ally correct became ever more difficult and time consuming It was to address verification challenges that what became hdls were first developed. Building on earlier work with proprietary simulation languages. Philip moorby and prabhu goel developed the first version of the verilog language in the winter of 1983 1984 at their then-young startup company Gateway. At the same time, several companies were developing the earliest logic syn thesis programs While it is implicit in the name(verilog is formed from the words verify logic) that the foci of efforts at gateway were simulation and verification, the language's designers from the beginning were intent on using it for circuit specification and synthesis Synopsys was the first to license the new language for circuit synthesis from HDL code. At the time, it was a symbiotic rela tionship, as Synopsys did not then sell simulators and gateway did not do logic synthesis Gateway was eventually bought by design automation company Cadence@, which does compete in the synthesis arena, and syn opsys has now long been in the simulation business as well as logic synthesis From its origins as a proprietary language verilog was released as an open standard in 1990 and in 1995 became an IEEE Standard IEEE 1364-1995. The standard has been updated and expanded several times, most recently by merging it with System Verilog,

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