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ARM® Architecture Reference Manual----ARMv7-A and ARMv7-R edition armv7-a和armv7-r官方手册,详细讲解了armv7a和armv7r的架构和新增特性。
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The right to use, copy and disclose this document may be subject to license restrictions in accordance with the lerIns of the agreement entered into by Arm and the parly that Arm delivered this document lo Product status The information in this document is final, that is for a developed product Web Address http://www.arm.cor ARM DDI 0406C d Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved D040418 Non-Confidential Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved ARM DDI 0406C d Non-Confidential D040418 Contents ARM Architecture reference manual arMmv7a and ARMV7-R edition Preface About this manual Using this manual… Conventions Additional readi XXI Feedback XXIV Part a Application Level Architecture Chapter a1 Introduction to the arm architecture A1.1 About the arm architecture A128 Al.2 The instruction sets A129 A1.3 Architecture versions, profiles, and variants A1-30 A1.4 Architecture extensions A1.5 The aRm memory model A1-35 Chapter A2 Application Level Programmers'Model A2. 1 About the Application level programmers model A238 A22 ARM core data types and arithmetic……… A2-40 A2. 3 ARM core registers A245 A2. 4 The Application Program Status Register(APSR) A249 A2.5 Execution state registers A250 A2. 6 Advanced SIMD and Floating- point Extensions A254 A2. 7 Floating-point data types and arithmetic A262 12.8 Polynomial arithmetic over 10, 11 A292 A2. 9 Coprocessor support .A293 ARM DDI 0406C d Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved D040418 Non-Confidential A2. 10 Thumb Execution environment A294 A2.11 Jazelle direct bytecode execution support A2-96 A2.12 EXceptions, debug events and checks A2.101 Chapter A3 Application Level Memory Model A3.1 Address space A3-104 A3.2 Alignment support A3-106 A3.3 Endian support A3-108 A3.4 Synchronization and semaphores A3.5 Memory types and attributes and the memory order mode/...... A3-112 A3-123 A3.6 Access rights A3-139 A3.7 Virtual and physical addressing A3-142 A3.8 Memory access order A3-143 A3. 9 Caches and memory hierarchy A3-153 Chapter A4 The Instruction Sets A4,1 About the instruction sets A4-158 A42 Unified Assembler Language A4-160 A4.3 Branch instructions A4.162 A44 Data-processing instructions……… A4-163 A4.5 Status register access instructions A4-172 A4. 6 Load/store instructions A4-173 A4.7 Load/store multiple instructions A4-175 A4.8 Miscellaneous instructions A4-176 A4.9 Exception-generating and exception-handling instructions A4-177 A4.10 Coprocessor instructions A4-178 A4.11 Advanced SIMD and Floating-point load/store instructions A4-179 A4.12 Advanced SIMD and Floating-point register transfer instructions A4-181 A4.13 Advanced sIMd data-processing instructions .. A4-182 A4.14 Floating-point data-processing instructions A4-189 Chapter a5 ARM Instruction Set Encoding A5. 1 ARM instruction set encoding A5-192 A5.2 Data-processing and miscellaneous instructions A5-194 A5.3 Load/store word and unsigned byte .A5-206 A5. 4 Media instructions A5-2 A5. 5 Branch branch with link and block data transfer A5-212 A5.6 Coprocessor instructions, and Supervisor Call A5-213 A5.7 Unconditional instructions A5-214 Chapter A6 Thumb Instruction Set Encoding A6. 1 Thumb instruction set encoding A6-218 A6.2 16-bit Thumb instruction encoding A6-22 A6.3 32-bit thumb instructi A6-228 Chapter A7 Advanced siMd and Floating- point Instruction Encoding A. 1 Overview A7-252 A7.2 Advanced SIMD and Floating-point instruction syntax A7-253 A7. 3 Register encoding A7-257 A7. 4 Advanced SIMD data-processing instructions A7259 A7.5 Floating-point data-processing instructions A7-270 A7.6 Extension register load/store instructions A7-272 A7. 7 Advanced simd element or structure load /store instructions A7-273 A7. 88, 16, and 32-bit transfer between arm core and extension registers..... A7-276 A7. 9 64-bit transfers between ARM core and extension registers A7-277 Chapter A8 Instruction Descriptions A8. 1 Format of instruction descriptions A8280 Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved ARM DDI 0406C d Non-Confidential D040418 A8.2 Standard assembler syntax fields A8285 A8.3 Conditional execution A8-286 A8. 4 Shifts applied to a register A8-289 A8.5 Memory accesses.. A8-292 A8.6 Encoding of lists of ARM core registers A8293 A8. 7 Additional pseudocode support for instruction descriptions A8-294 A8.8 Alphabetical list of instructions A8-298 Chapter A9 The thumbeD Instruction Set a9. 1 about the thumbed instruction set A9-1112 A9.2 ThumbEE instruction set encoding A9-1115 a9.3 Additional instructions in thumb and thumbed instruction sets A9-1116 a9. 4 Thumbee instructions with modified behavior .A9-1117 a9.5 Additional thumbed instructions A91123 Part B System Level Architecture Chapter B1 System Level Programmers'Model B1.1 About the System level programmers model B1-1134 B1.2 System level concepts and terminology .B11135 B1.3 ARM processor modes and ARM core registers B1-1139 B1.4 nstruction set states B1-1155 B1.5 The Security Extensions…........… B11156 B1.6 The Large Physical Address EXtension B11159 B1.7 The virtualization extensions B1-1161 B1.8 Exception handling B11164 B1.9 Exception descriptions B1-1204 B1.10 Coprocessors and system control B1-1225 B1.11 Advanced SIMD and floating-point support B1-1228 B1.12 Thumb execution environment B11239 B1.13 Jazelle direct bytecode execution B1-1240 B1.14 Traps to the hypervisor B1-1246 Chapter B2 Common Memory System Architecture Features B2. 1 About the memory system architecture B21262 B2.2 Caches and branch predictors B2-1264 B2.3 IMPLEMENTATION DEFINED memory system features B2-1290 B2. 4 Pseudocode details of general memory system operations B2-1291 Chapter B3 Virtual Memory System Architecture(VMSA) B3.1 about the vmsa B3-1306 B3.2 The effects of disabling mmus on visa behavior B3-1312 B3.3 Translation tables B3-1316 B3.4 Secure and Non-secure address spaces .B3-1320 B3.5 Short-descriptor translation table format B3-1321 B3.6 Long-descriptor translation table format B3-1334 B3.7 Memory access control B3-1352 B3.8 Memory region attributes B3-1362 B3. 9 Translation Lookaside Buffers(TLBs B3-1374 B3. 10 TLB maintenance requirements B3-1377 B3. 11 Caches in a VMSa implementation.. B3-1389 B3.12 VMSA memory aborts B3-1392 B3. 13 Exception reporting in a VIsa implementation B3-1406 B3. 14 Virtual address to physical Address translation operations B3-1434 B3.15 About the system control registers for VMSA B3-1440 B3. 16 Organization of the cP 14 registers in a VIsa implementation B3-1464 B3. 17 Organization of the CP1 5 registers in a VMSA implementation B3-1465 ARM DDI 0406C d Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved D040418 Non-Confidential B3.18 Functional grouping of VMSAv7 system control registers B3-1486 B3.19 Pseudocode details of VMsa memory system operations B3-1498 Chapter B4 System Control Registers in a VMSa implementation B4.1 VMSA System control registers descriptions, in register order B4-1518 B4.2 VMSA system control operations described by function B4-1735 Chapter b5 Protected Memory System Architecture(PMSA) B5.1 About the pmsa B5-174 48 B5. 2 Memory access control B5-1753 B5.3 Memory region attributes B5-1754 B5. 4 PMSa memory aborts B5-1757 B5.5 EXception reporting in a PMSa implementation .B5-1761 B5.6 About the system control registers for PMSa B5-1766 B5.7 Organization of the CP14 registers in a PMsa implementation B5-1778 B5.8 Organization of the cP15 registers in a Pmsa implementation B5-1779 B5. 9 Functional grouping of PMSAv7 system control registers B5.10 Pseudocode details of Pmsa memory system operations….……… B5-1791 B5-1798 Chapter B6 System Control Registers in a PMsa implementation B6.1 PMSA System control registers descriptions, in register order B6-1802 B6.2 PMSA system control operations described by function B6-1932 Chapter B7 The CPuid Identification scheme b71 ntroduction to the cpuid scheme B71938 B7.2 The CPUID registers B7-1939 B7.3 Advanced SIMD and Floating-point EXtension feature identification registers B7-1944 Chapter B8 The Generic Timer B8.1 About the generic timer B8-1946 B8.2 Generic T imer registers summary B8-1955 Chapter b9 System Instructions B9. 1 General restrictions on system instructions B9-1958 B9. 2 Encoding and use of Banked register transfer instructions B9-1959 B9.3 Alphabetical list of instructions B91964 Part c Debug Architecture Chapter C1 Introduction to the ARM Debug architecture C11 Scope of part C of this manual C1-2008 C1.2 About the ARM Debug architecture C12009 C1.3 Security Extensions and debug…………… C12013 C1.4 Register interfaces C12014 Chapter c2 Invasive Debug Authentication C2. 1 About invasive debug authentication C22016 C2. 2 Invasive debug with no Security Extensions C22017 C2. 3 Invasive debug with the security EXtensions C22019 C2.4 Invasive debug authentication security considerations C22021 Chapter C3 Debug Events C3. 1 About debug events c3-2024 C3.2 BKPT instruction debug events C3-2026 3.3 Breakpoint debug events C32027 C3.4 Watchpoint debug events C32045 Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved ARM DDI 0406C d Non-Confidential D040418 C35 Vector catch debug events…… C3-2053 C3.6 Halting debug events C3-2061 C3.7 Generation of debug events C3-2062 C3. 8 Debug event prioritization C32064 C3.9 Pseudocode details of Software debug events C32066 Chapter C4 Debug Exceptions C4.1 About debug exceptions C42076 C4.2 AVoiding debug exceptions that might cause UNPREDIC TABLE behavior ..C4-2078 Chapter C5 Debug state C5.1 About Debug state .C5-2080 C52 Entering Debug state c52081 5.3 EXecuting instructions in Debug state c5-2084 C54 Behavior of non-invasive debug in Debug state C5-2092 C55 Exceptions in Debug state c5-2093 C5.6 Memory system behavior in Debug state C5-2097 C57 Exiting Debug state C5-2098 Chapter C6 Debug Register Interfaces C6. 1 About the debug register interfaces C6-2102 C62 Synchronization of debug register updates C6-2103 C6.3 Access permissions C6-2105 C6. 4 The CP14 debug register interface .C6-2109 C6. 5 The memory-mapped and recommended external debug interfaces.... C6-2114 C6.6 Summary of the v7 Debug register interfaces c62116 C6.7 Summary of the v7. 1 Debug register interfaces C6-21 Chapter C7 C7.1 Debug Reset and Powerdown support C7.1 Debug guidelines for systems with energy management capability .C7-2136 C7. 2 Power domains and debug C7-2137 C7.3 The os save and restore mechanism .C7-2140 e7.4 Reset and debug c7-2148 Chapter C8 The Debug communications Channel and Instruction Transfer Register c8.1 About the dcc and dbgitr c82152 C8.2 Operation of the dCC and Instruction Transfer Register c82155 C8.3 Behavior of accesses to the dcc registers and dBGITR. ........... C8-2159 C8.4S ynchronization of accesses to the dcc and the dBgitr C8-2164 Chapter c9 Non-invasive Debug Authentication C9. 1 About non- invasive debug authentication C92170 C9.2 Non-invasive debug authentication .C9-2171 C9.3 Effects of non- invasive debug authentication…………… C9-2173 Chapter C10 Sample-based Profiling C10.1 Sample-based profiling C10-2176 Chapter C11 The Debug Registers C11.1 About the debug registers C11-2180 C11.2 Debug register summary C112181 C11. 3 Debug identification registers C11-2184 C11.4 Control and status registers C112185 C11.5 Instruction and data transfer registers .C112186 C11.6 Software debug event registers C112187 C11.7 Sample-based profiling registers C112188 C11.8 OS Save and Restore registers C11-2189 ARM DDI 0406C d Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved X D040418 Non-Confidential C11.9 Memory system control registers C11-2190 C11.10 Management registers C112191 C11.11 Register descriptions, in register order C112197 Chapter C12 The Performance monitors extension C12.1 About the performance monitors .C12-2288 C12.2 Accuracy of the performance Monitors C12-2292 C12.3 Behavior on overflow C122293 C12.4 Effect of the Security EXtensions and Virtualization Extensions.......C12-2295 C12.5 Event filtering, PMUV2 C12-2297 C12. 6 Counter enables C122299 C12.7 Counter access .C122300 C128 Event numbers and mnemonics C12-2301 C12.9 Performance Monitors registers C12-2314 Part D Appendixes Appendix A Recommended External Debug Interface D1.1 About the recommended external debug interface D1-2324 “““a D1.2 Authentication signals D1-2326 D1.3 Run-control and cross-triggering signals .D1232 D1.4 Recommended debug slave port D1-2332 D1.5 Other debug signals D1-2334 Appendix b Recommended Memory-mapped and External Debug Interfaces for the Performance Monitors D2. 1 About the memory-mapped views of the Performance Monitors registers ... D2-2340 D2.2 PMU register descriptions for memory-mapped register views D2-2349 Appendix c Recommendations for performance monitors Event numbers for IMPLEMENTATION DEFINED EVents )3. 1 ARM recommendations for imPlEMEntation DEfined event numbers D3-2364 Appendix D Example os save and restore sequences for External debug over Powerdown D4.1 Example OS Save and Restore sequences for v7 Debug .......... D4-2376 D4.2 EXample os Save and Restore sequences for v7. 1 Debug D4-2380 Appendix E System Level Implementation of the Generic Timer D5. 1 About the Generic Timer specification D5-2384 D52 Memory-mapped counter module D5-2385 D53 Counter module control and status register summary D5-2388 D5. 4 Memory-mapped timer components D5-2390 D5.5 The cntbasen and cntplobasen frames D5-2391 D5. 6 The CNTCTlBase frame .D5-2393 D57 System level Generic Timer register descriptions, in register order D5-2394 D58 Providing a complete set of counter and timer features D5-2411 D5. 9 Gray-count scheme for timer distribution scheme D5-2413 Appendix F Common VFP Subarchitecture Specification D6.1 Scope of this appendix D6-2417 D6.2 Introduction to the common vfp subarchitecture.............. D6-2418 D63 Exception processing D6-2420 D6.4 Support code requirements a:“ D6-2424 D65 Context switching D6-2426 D6.6 Subarchitecture additions to the Floating-point EXtension system registers..D6-2427 X Copyright@ 1996-1998, 2000, 2004-2012, 2014, 2018 ARM Limited. All rights reserved ARM DDI 0406C d Non-Confidential D040418


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