ADS 过孔仿真

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4. Open a layout cell by clicking on layout icon in the main ads window e or by selecting File->New->Layout from the main ads window 5. Click on Substrate icon present in the em toolbar of the layout window and select oK in the pop window which 1 intimates us that there is no substrate present and then we select default substrate as a template for our own substrate stackup creation once done a default microstrip substrate would be available as shown below AIR metall Aum ina 5 mil 0 mil 6. Right click on Alumina substrate and select option "Insert Substrate Layer above, repeat it to add 5 dielectric layers as shown below AIR 125 Alumina 100 umina 75 Amir 25 mil 鸟 umIna metali mIna il 7. Right click on the bottom cover and select"Delete Cover"to remove the infinite ground lane from the bottom left click on lowest alumina and select the material to be air 8. Click on the substrate interface above metall and select the interface to be slot plane (SLOT is a negative ground plane in ADS). Repeat the same for 2 more interfaces 9. Right click on interface above metall and select"Map SLoT Layerand notice that metal2 is mapped to this interface. Repeat the same at 2 interfaces above to see metal3 and metal4 getting mapped 10. Right click on the topmost interface and select Map conductor layer and see metal5 will be mapped as conductor making it toP conductor as shown in the next snapshot metaLs 100 5 mil metal metal3 y met=l2 HumIna etal 11. Now we have conductors on top and bottom layer and need to define the via mapping between these conductors We can either create a stacked via or a thru via definition for simulation results it really doesnt matter and layout designers make it based on their convenience. In this case study we shall use stacked via definition and for that we need to have a separate via layer on each dielectric. 12. Right click on the substrate between metal5 and metal4 and select "Map Conductor VIA and notice that" layer is mapped as via between metal5 and metal4 layer repeat it or all the substrate layers to see via 2, via 3 and via4 getting mapped as shown below AIR meta5 100 Lumina mil ial metala 50 numina . 5 mil tal2 Alumina metall o mil AIR It is good time to recall that we define process role for these layers and they were having layer numbers assigned when we created them and it helps ads to assign these layers during substrate creation in increasing layer number order and keep track if we are mapping conductors or VIAs. Even if we do not define a process role we can always change the layer name once the object (i.e. conductor or via) is mapped to dielectric stackup but that would require little manual work. 13. Now we have the stackup detinition ready, remaining thing is to specify the material properties and thickness etc. click on each substrate stackup layer shown as Alumina and define the thickness as 5 mils 14. Click on Technology->Material Definitions and in the dielectric Tab, click on Add from Database and select fr4 from the list and click ok 15. Go to Conductor tab and select Copper from available conductors list and click OK 16. Click oK on the material definition window and select each dielectric layer and change the material to fR4 as shown below Substrate Name: subsTa E 2 Use right mouse context menus to adc or delete s ubstrateitems Select items on the substrate and viEw - heir properties below Substrate Layer Material FR4 ding area layer: <undefined>c) Ha3 meal 17. Click on metal 1 and select material as Copper, thickness as 35um, Operation as "Intrude into substrate and position as below interface"so that this metal is defined as thickness of 35um which is growing on the lower side of the stackup 18. Click on metal5 and select material as Copper thickness as 35um, Operation substrate"and position as"Above interface"as we want it to grow upwards as"Intrude into 19. Once done dielectric stackup will appear as shown below 15 F卩4 metals 1 M3s 4 Using multilayer via utility in ADs: 1. From the layout window, select Add-Ons ->Via Drawing Utility 2. In the pop-up window of via drawing utility select 5 layers 3. Select metal5 downwards to metall against each conductor (as per our stackup definition) 4. Select vial to via 4 against each dielectric layer. 5. Define metall and metal5 type as signal and rest as slot plane as shown below Board Layers ayer Type Conductor 1 metal5 Signal Dielectric 1 VIa1 Conductor 2 metal4 v Slot Plane Dielectric 2 via D 3 Layers Conductor 3 metal3 Slot Plane Dielectric 3 via3 E lAyers Conductor 4 metal2 Slot Plane Dielectric 4 via4 回5 o Layers Conductor.met Siana 6. In the board outline define board outline dimension of width=400 and length=600 and select layer as ads supply (this is only to draw the board outline 7. Define all hole diameters as 16 with Signal pad on metall and 5 layer 24, antipad dimensions for slot layer as 40 8. Define via type as differential with Spacing as 50 and select Ground via as center to draw a ground via between the Differential VIAs 9. Under Connecting Traces, define the parameters as shown here onnecting races Trace Width Traces spacing Tr Tac= An Corner Type Curve radius Upper 10 25 Curve 15 5 45 5 10. Once done it will appear as belo All length waues are in sycut un ts. In he current visN this is Dcarc outine Width 400 Length 600 Layer ads_supEly TEC Hole diameter Pad dieme-cr Anti pad diameter Conducto1 meta 5 君 Conduct”2mta4 5b:叫 Plane Fl6 Dielectric 2 2 回3acot+met3sse1612 回4 ers Cunuulu'4Iml2sh.an-16 Dielectric 4 v_ayers Conductors meta 1 a sayers Cumulu E 7 Sturla Dielectric 5 回7 ayers conductor7 8_aye Conductors 24 SigrId Vids Ground vids Single o) Differential Join Anti-Pads V Center Spacing Nerica offset Connecting Traces Ti dLe wiu山 Tdssψdur TidLe Anue Cor tl=r ype CurveR-ujus Lower 10 3 Lrwe 11. Click on Draw to see differential ViA geometry drawn in ADS layout as shown below EM 12. Click on EM Setup icon in the EM Toolbar Demc_Multilayer_VIAuti ity_ib: cell_2: emSetup(EM Setup 口回 File Tools view Help 回、爵囚国⑩國 EM Mom uw Simu ator 3 layout ○ Momer tm eF o Momentum Microwave FEM E Substrate Setup Overview rcy plai Simulator ri Output plan Momen um sinulation ir microwAVE mode Tall WorkspacE: C: UEers antharga DS 2012 Workspaces Deno Multilayer IAutility wrk brary: Demo Multiayer vIAu lity b Resources ViEW: layout Substrale Substrate: substrate defined in I brary: Demo Mutilayer VIAL tility lib) urls. 4 ports detined FrequentLy plaIN: Adaptive from 0 GHz to 10 GHz Npts: 50 (max)) uLpul plai Datase;ce‖2 Monli Mom Simulation options Al simu ation options are initialized and ready for sinulation Simulation sources mulation an host: Loce Auto-create EM Mode: no EM Mocel; emMcdel Auto-create sym bol: nc Symbol: symbol ererate:S-Parameters Click on 3D View icon to inspect geometry in isometric fashion as shown below a. Select on Mom uW and select Simulator as Momentum rf this is quasi static mode which is ideally suited for electrically small structures as VIAs. Momentum Microwave can also be selected but RF mode would be faster and produces quite accurate results for geometries which are less than half-wavelengths. b. Click on Substrate and make sure we are using our 5 layer stackup definition C. Click on Ports to ensure there are 4 ports connecting between P1-4 to Gnd. GNd here is reference to the slot planes which are negative ground reference planes d. Click on Frequency plan and define the frequency sweep from 0-10 GHz with 50 (max) points and Adaptive Sweep e. Click on Options and go to mesh Tab and enter Cells/ wavelength =50 to ensure enough cells for accurate computation for larger geometries default value of 20 is quite sufficient however for smaller geometries such as present case we need to change it to little higher number such as 50 or 100 for little denser mesh f. Click on Simulate icon to start the em simulation and it will take couple of minutes to compute Substrate's Green Functions (one time)and simulation will finish in less than a minut 13. Once the simulation is finished, data display window as shown here would be available with the simulation results H 14. Close the data display window and go to EM setup window again and change the simulator to fem 15. Click on Options->Mesh->Stop Criterium as 0.02(delta error in S-matrix for mesh to converge as shown in next snapshot Simulation Options opr as… Rename Remove Description Physical Model PreprocessorMeshSolverExpert Stop criterium [ ReienlenL T Tilel Me:[AdvalLed1 Delta :0.02 Consecutive passes of delta error requirec: 1 Minimum rumber of adaptive passes:2 Maximum rumber ot adaptive gasses: 15 □ Use memcry linit V Automatically open mesh convergence pot 16. Click on simulate button and see that fem simulator is invoked to simulate the via structure and now it takes some time to simulate the structure and it is not as fast as momentum re simulator 17. Once FEM simulation is finished a new data display will be opened with FEM simulation 18. Once we plot Momentum and FEm simulation results on these graphs, below is the comparison MagnItude [aB] freq, CH fre g GHz freq GHz treq. GH Here, red traces are fem simulation results and blue indicates momentum simulation results and it can be seen that Momentum and FEM simulation results are pretty close and we can use Agilent Momentum for accurate multilayer ViA simulations as it is lot faster in simulating multi-layer VIA structures as compared to FEM

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