UZ2400 datasheet(Transceiver for IEEE802.15.4)

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Low Power 2.4 GHz Transceiver for IEEE 802.15.4 Standard
Buber a Home/ Building/Factory Automation a 2-way Medium-Data-Rate Application a Wireless sensor network 彐 PC Peripheral 彐 RF Remote Contro!er Consumer electronics Low power wireless communication a Advanced Meter Infrastructure(AMI) UZ2400 Silicon Version d is a solution that complies with IEEE 802. 15. 4-2006 specif ications. It integrates a 2.4 ghz rf transceiver with an IEEE802. 15.4 compliant Baseband/Mac block within a single chip the UZ2400 can be controlled by a microprocessor(e. g. 8051) for low-data-rate applications such as home automation, industrial automation, consumer electronics, PC peripheral .etc. For medium-data-rate applications like wireless voice and image transmission, the UZ2400 provides 1M/2M bps turbo mode The rf block of the UZ2400 integrates receiver, transmitter, voltage-controlled oscillator (vco), and phase-locked loop(PLL). It uses advanced radio architecture to minimize the external component count and the power consumption. The Baseband/MAC block provides the hardware architecture for both IEEE 802. 15. 4 compliant MAC and PHY layers. It mainly consists of TX/RX control, CSMA-CA controller, Superframe constructor, security engine and digital signal processing module. The uZ2400 is fabricated with the 0.18um advanced rFCMos process and is sealed in a 40-pin QFN 6X6 mm package ISM band 2.40502.480 GHz operation o Integrated 32 MHz and 32 768 KHz oscillator J IEEE 802.15.4-2006 specif ication compliance drive J-95 dbm sensitivity and 3 dBm max input level u integrated internal oscillator circuit 0 d Bm typical output power and 40 dB TX d 32 MHz reference clock output power control range a Digital vco and filter calibration a Differential RF input/output and integrated a Integrated RSSi ADC and I/Q DACs TX/RX SWitch a Integrated dc-DC converter a Integrated low phase noise vco, frequency o 1M/2M bps turbo mode supported Q o High receiver and rssi dynamic range synthesizer and PLl loop filter DS-2400-51<ReV.0.5> page 3/176 ubec a Low current consumption 16 mA in RX and a Small 40-pin leadless QFn 6x6 mm package 17. 5 mA in Tx mode o 0.18 um RF CMOs technology 彐2.4 ua deep sleep mode Low external component count IEEE 802.15.4-2006 specification compliance 口Dua| RX FIFOS Hardware CSMA-CA mechanism automatic a Hardware security engine(AES-128 ACK response and FCs check arious power saving modes a Programmable Superframe construction a Support all CCa modes and Rssi/LQI a Functionally independent TX FIFOs, including a Simple four-wire SPI interface beacon Fifo, transmit fifo and gts fifos I-C slave supported Figure 1 shows the block diagram of the UZ2400. It is composed of six blocks: 彐 PHY bloc 彐 Security engine block a Lower mac block o Power management block 彐 Memory block 彐 Interfacing block Detailed descriptions for each block will be described in Chapter 3 of this datasheet Lz2400 erasing Block Figure 1: UZ2400 block diagram DS-2400-51<ReV.0.5> page 4/176 Buber Applications…. Introduction Features 3334 Block diagram.… 1. Pin Configuration∴ ■面面 11 1.1. Device Pin Assignments……… 1.2 Device pin descriptions ,12 2 Electrical characteristics 141 2. 1. Absolute Maximum Ratings .14 2. 2. Recommended Operating Conditions 14 2. 3. DC Electrical Characteristics 14 2. 4. Radio frequency Ac characteristics 15 24.1. Receiver Radio frequency Ac characteristics.…,…,…,…,……,15 24.2. Transmitter Radio Frequency Characteristics,…,,…,… ∴15 25, ESD Notice 16 2.6. Peripheral characteristics…,,,,,,,… 16 2.7. Power-on and Reset characteristics 16 2. 8. Crystal Parameter Specifications 16 3. Functional Description 17 3. 1. PHY Block 3. 1.1. IEEE 802.15 4-2006 PHY Introduction 18 3.1.2. The phy enhancement of the uz2400…… 18 3.1.3. RSSI/ED and LQI 19 3.1.4.CCA 3. 2 Lower mac block 19 3.2.1. IEEE 802.15.4-2006 MAC Introduction 3.2.2. MAC Timer 23 3.2. 3. RXMAC 23 3.2.4. TXMAC 26 3.2.5 CSMA-CA ■量 26 3.3. Memory block.. 29 3.3.1. Registers eemeeee.I. 30 3.3.2. FIFOs 30 3. 4. Power Management Block 32 3. 4.1. Power Supply Scheme 画B国面画面面 32 3.42. DC-DC Converter OFF Mode and dc-DC Converter on/ Bypass Mode………,……3 3.4.3. Battery monitor 34 3. 44. Power-on Reset 34 3. 4.5. Power Saving Modes 34 3.4.6. Counters for Power Saving Modes . 35 3.4.7 Hardware Acknowledgement 38 3.5. Security Engine block.. 3.6. Analog Circuits DS-2400-51<ReV.0.5> page 5/176 ubec 3.6. 1. Crystal Oscillators 3.6.2. PLL Frequency Synthesizer 3.6.3. Internal Oscillator for Sleep Clock ∴41 3.6.4. 32.768 kHz Crystal Oscillator for the sleep Clock 41 3.7. Peripherals… 41 3. 7.1. SPI Interface 3,7.2.12 C Interface… n44 3.7.3 GPIO 3.74. Interrupt signal,…,… 日面L面面面面面 11I面面面B面B面道 ,46 4. Application guide 4.1. Hardware Connection 48 4.2. Registers and FIFos…… 49 4.21. Memory space… 49 4.2.2. Register Summary ∴…49 4.2.3. Security Key FIFo 53 4.3. Basic Operations. .......... 4.3.1. Initialization 53 4.3.2. Clock Recovery Time 4.3.3. Change channel procedure 256 4.3.4. Interrupt Configuration 4.3.5. External Power Amplifier Configuration 4.36. Turbo Mode Configuration………… 4. 4. Typical TX Operations ∴59 4.4.1 Transmit Packet in normal fifo 4.4.2 Transmit Packet in gTS FiFo 60 4.4.3. Transmit Packet with Security Encryption 61 4.4.4. transmit Packet in Normal FIFO with CCA/ED mode or combination of CS and ED modes. 63 4.5. Typical RX Operations 64 4.5.1. Receive Packet in RXFIFo 64 4.5.2. Receive Packet with Security Decryption 64 4.6. Beacon Mode operations 6 4.61. Beacon Mode setting…,…, 66 4.6.2. Beacon Mode GTS Setting.. 71 4.7. Power Saving Operations 4.7.1. Wake-up Operations 73 4.7.2. Power saving operations 74 4.8. Battery Monitor Operations 76 4.9. Upper-Layer-Cipher Operations 76 4.9.1. Upper- Layer-Cipher Encryption…… ∴76 4.9.2. Upper-Layer-Cipher Decryption 5. Package Information 82 51. Package Drawing,…,…,… 8 5. 2. Package Soldering 84 5.2.1. Background. 84 5.2.2. Reference Reflow Temperature Curve... n.84 DS-2400-51<ReV.0.5> page 6/176 Buber Appendix A. RSSI mapping table,,,…,… 85 Appendix B. TX Power Configuration 87 Appendix C register Descriptions 88 C 1 Short Registers(SREGOXOON SREGOX3F) C 2 Long Registers(LREGOX200NLREGOx27F) 130 DS-2400-51<ReV.0.5> page 7/176 Buber ACK Acknowledgement ADC Analog to digital Converter AES Advanced Encryption Standard CAP Contention Access period CBC-MAC Cipher Block Chaining Message Authentication Code CCA Clear Channel Assessment CCM Counter channel mode CFP Contention free period CSMA-CA Carrier Sense Multiple Access with Collision Avoidance CRC Cyclic Redundancy Check CTR Counter mode cbc Direct Sequence Spread Spectrum ESI Electronic Static Discharge EVM Error Vector Magnitude FCF Frame Control Field FCS Frame Check Sequence FIFO First in first out GTS Guaranteed Time slot IEEE Institute of Electrical and electronics engineers INT Interrupt ISM Industrial scientific and medical ITU-T International Telecommunication Union-Telecommunication I/O Input/Output I/Q In-phase/ Quadrature-phase Kbps Kilo bit per second LNA Low Noise Amplifier Local oscillator LQf Link Quality Indication LSB Least Significant Bit Byte MSB Most signif icant Bit / Byte MAC Medium access control MIC Message Integrity Code NA Not available NC Not connected O-QPSK Offset Quadrature Phase Shift Keying PA Power amplifier PCB Printed Circuit Board PHY Physical Layer Phase Locked Loop QFN Quad Flat No-lead Package RF Radio frequency Receive Signal Strength Indicator RⅩ Receive DS-2400-51<ReV.0.5> page 8/176 ubec SPI Serial Peripheral Interface SED Start-of-Frame delimiter TBD To Be defined IX Transmit VCO Voltage Control Oscillator 1. SREGOXnn[m] or SREGOXnn[p: m] SREG: short register Onr ister number nn: can be numerical numbers(for example: 1, 2, or 3, etc)or alphabetical words(for example: A, b, or 1: the bit number Ip: m]: bit m, bit n, bit o, and bit p( for example: bit[7: 5] means bit 7, bit 6, bit 5, and bit 4) 2. LREGOXnn[] or LREGOXnn[p: m] LREG: long register Oxnn: register number nn: can be numerical numbers(for example: 1, 2, or 3, etc)or alphabetical words(for example: A, b, or m]: the bit number Lp: m]: bit m, bit n, bit o, and bit p(for example: bit[ 7: 5] means bit 7, bit 6, bit 5, and bit 4 DS-2400-51<ReV.0.5> page 9/176 Buber DS-2400-51<Rev.0.5> page10/176

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