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P3041 QorIQ Integrated Multicore

Communication Processor Family

Reference Manual

Document Number: P3041RM

Rev. 0, 11/2011

Contents

Section Number Title Page

Chapter 1

Overview

1.1 Introduction...................................................................................................................................................................71

1.2 QorIQ P3041 Features..................................................................................................................................................71

1.3 Block Diagram..............................................................................................................................................................72

1.4 P3041 Multicore Processing Options............................................................................................................................73

1.4.1 Running on an OS......................................................................................................................................73

1.4.2 Running OS-Less Using a Simple Scheduler............................................................................................74

1.5 DPAA Multicore Processing Options...........................................................................................................................74

1.6 QorIQ P3041 Applications...........................................................................................................................................76

1.7 Subsystem Features.......................................................................................................................................................78

1.7.1 e500mc Core and Cache Memory Complex..............................................................................................78

1.7.1.1 e500mc Core Features............................................................................................................78

1.7.1.2 128-Kbyte Private Backside Cache........................................................................................79

1.7.1.3 CoreNet Platform Cache (CPC).............................................................................................79

1.7.2 CoreNet Fabric and Address Map..............................................................................................................80

1.7.3 Memory Complex......................................................................................................................................80

1.7.3.1 DDR Memory Controller.......................................................................................................80

1.7.3.2 PreBoot Loader and Nonvolatile Memory Interfaces............................................................81

1.7.3.2.1 Enhanced Local Bus Controller......................................................................81

1.7.3.2.2 Serial Memory Controllers.............................................................................82

1.7.4 Universal Serial Bus (USB) 2.0.................................................................................................................82

1.7.5 High-Speed Peripheral Interface Complex................................................................................................83

1.7.5.1 PCI Express Controllers.........................................................................................................83

1.7.5.2 Serial RapidIO........................................................................................................................83

1.7.6 Serial ATA (SATA)2.0 Controllers ..........................................................................................................85

P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. 0, 11/2011

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Section Number Title Page

1.7.7 Data Path Acceleration Architecture (DPAA)...........................................................................................86

1.7.7.1 Data Path Acceleration Architecture (DPAA) Programming Model.....................................87

1.7.7.2 Definitions..............................................................................................................................88

1.7.7.3 Packet Walk Through.............................................................................................................89

1.7.7.4 Major DPAA Components.....................................................................................................91

1.7.7.5 Frame Manager......................................................................................................................92

1.7.7.5.1 Network Interfaces..........................................................................................92

1.7.7.5.2 Parse Function.................................................................................................93

1.7.7.5.3 Distribution and Policing................................................................................93

1.7.7.6 Queue Manager......................................................................................................................94

1.7.7.7 Buffer Manager......................................................................................................................95

1.7.7.8 Security Engine (SEC 4.2).....................................................................................................95

1.7.7.9 Pattern Matching Engine (PME) 2.1......................................................................................97

1.8 Resource Partitioning and QorIQ Trust Architecture...................................................................................................98

1.8.1 e500mc MMU and Embedded Hypervisor................................................................................................99

1.8.2 Peripheral Access Management Unit (PAMU)..........................................................................................99

1.8.3 Secure Boot and Sensitive Data Protection................................................................................................100

1.8.3.1 Secure Boot Option................................................................................................................100

1.8.3.2 Sensitive Data Protection Option...........................................................................................100

1.9 Advanced Power Management.....................................................................................................................................101

1.9.1 Saving Power by Managing Internal Clocks..............................................................................................101

1.9.2 Turning Off Unneeded Clocks...................................................................................................................101

1.9.3 Avoiding Full System Failure Due to Thermal Overload..........................................................................101

1.10 Debug Support..............................................................................................................................................................102

Chapter 2

Memory Map

2.1 Memory Map Overview................................................................................................................................................105

2.2 Global Source and Target IDs.......................................................................................................................................106

P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. 0, 11/2011

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Section Number Title Page

2.3 Local Access Windows (LAWs)..................................................................................................................................108

2.3.1 Precedence of Local Access Windows......................................................................................................108

2.3.2 Configuring Local Access Windows.........................................................................................................109

2.3.3 Distinguishing Local Access Windows from Other Mapping Functions..................................................109

2.3.4 SRAM Windows........................................................................................................................................110

2.3.5 Local Address Map Example.....................................................................................................................110

2.4 Local Access Window (LAW) Memory Map..............................................................................................................112

2.4.1 LAWn base address register high (LAW_LAWBARHn).........................................................................115

2.4.2 LAWn base address register low (LAW_LAWBARLn)...........................................................................115

2.4.3 LAWn attribute register (LAW_LAWARn)..............................................................................................116

2.5 Address Translation and Mapping Units......................................................................................................................117

2.5.1 Address Translation ..................................................................................................................................117

2.5.2 Outbound ATMUs.....................................................................................................................................118

2.5.3 Inbound ATMUs........................................................................................................................................118

2.5.3.1 Illegal Interaction Between Inbound ATMUs and LAWs.....................................................119

2.6 Configuration, Control, and Status Register (CCSR) Space.........................................................................................119

2.6.1 Accessing CCSR Memory from the Local Processor................................................................................119

2.6.2 Accessing CCSR Memory from External Masters....................................................................................120

2.6.3 Accessing Reserved Registers and Bits.....................................................................................................120

2.6.4 Organization of CCSR Memory................................................................................................................120

2.6.5 CCSR Address Map...................................................................................................................................121

Chapter 3

Signal Descriptions

3.1 Introduction...................................................................................................................................................................127

3.2 Signals Overview..........................................................................................................................................................127

3.3 Dedicated Configuration Signals..................................................................................................................................138

3.3.1 I/O Voltage Select......................................................................................................................................138

3.4 Configuration Signals Sampled at Reset.......................................................................................................................139

P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. 0, 11/2011

Freescale Semiconductor, Inc. 5