`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:24:41 12/26/2012
// Design Name:
// Module Name: pwm_led
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm_led(
clk,led,rst
);
input clk;
input rst;
output [7:0] led;
reg [7:0] led;
reg [19:0] cnt;
always @ ( posedge clk )
begin
if(!rst) begin
cnt <= 0;
end
else begin
if(cnt==1000000-1)
begin
cnt <= 0;
end
else begin
if(cnt<10000)
led[7] <= 0;
if(cnt>=10000)
led[7] <= 1;
end
cnt <= cnt+1;
end
end
always @ ( posedge clk )
begin
if(!rst) begin
cnt <= 0;
end
else begin
if(cnt==1000000-1)
begin
cnt <= 0;
- 1
- 2
前往页