module count_smg(
input CLK,
input RST,ENA,key_clk,
output [7:0]SMG_data,
output scan_sig,count
);
wire [3:0]SL;
count_10 u3(
.RST(RST),
.SL(SL),
.key_clk(key_clk),
.ENA(ENA),
.count(count)
);
smg_interface u4 (
.CLK(CLK),
.RST(RST),
.SL(SL),
.SMG_data(SMG_data),
.scan_sig(scan_sig)
);
endmodule
module count_10(input fre,RST,ena,rst_count,output [3:0] MSH,MSL,SH,SL);
reg [3:0] MSH,MSL,SH,SL;
reg f;
reg [19:0] rst_count;
always @(posedge fre or posedge RST)
begin
if(RST||rst_count)
begin
MSH<=0;
MSL<=0;
SL<=0;
SH<=0;
end
else if(ena)
begin
if(MSL==9)
begin
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