stm32f030参考手册

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stm32f030参考手册,寄存器描述,外设
Contents 3.5.8 Write protection register(FLASH WRPR) 54 3.6 Flash register map ■■■ 55 Option bytes ..,.. 56 4.1 Option byte description 57 4.1.1 User and read protection option bytes .....57 4.1.2 User data option bytes .58 4.1.3 Write protection option bytes 58 4.1. 4 Option byte map 59 5 Cyclic redundancy check calculation unit CRC) 60 5.1 Introduction 60 5.2 CRC main features 60 5.3 CRC functional description 6 5.4 CRC registers 62 5.4.1 Data register(CRC_ DR) 62 5.4.2 Independent data register (CRC IDR) 63 5.4.3 Control register(CRC CR) ..63 5.4.4 Initial CRC value(CRC_INIT) ..64 5.4.5 CRC register map ....,64 Power control (PWR) 65 6.1 Power supplies 65 6.1.1 Independent A/D converter supply and reference voltage 65 6.1.2 Voltage regulato 6.2 Power supply sup 6.2.1 Power on reset(POR)/power down reset(PDR 6.3 Low-power modes .......... 67 6.3. 1 Slowing down system clocks 68 6.3.2 Peripheral clock gating 6.3.3S|e 69 6.3.4 Stop mode 70 6.3.5 Standby mode 72 6.3.6 RTC wakeup from low-power mode 6.4 Power control registers 74 6.4.1 Power control register(PWR CR) ...,.,74 DocID025023 Rev 1 3/655 Contents 6.4.2 Power control/status register(PWR CSR) 75 6.4.3 PWR register map 76 Reset and clock control(Rcc) ■量■■■■■■■■■■■ ,,,77 7.1 Reset 7.1.1 Power reset 7.1.2 System reset 7.1.3 rtc domain reset 78 7. Clocks...... ..,79 7.2.1 HSE clock 7. 2.2 HSI clock ..,.82 7.2.3PLL .83 7.24 LSE clock 7.2.5 LSI clock 4 7.2.6 System clock(SYSCLK)selection 84 7. 2.7 Clock security system(CSS) 84 7. 2.8 ADc clock 85 7. 2.9 Rtc clock 85 7.2.10 Independent watchdog clock 翻 ....,85 7. 2. 11 Clock-out capability 86 7.2.12 Internal/external clock measurement with tIM14 86 7.3 Low power modes......,.....,....................87 7.4 RCC registers 89 7.4.1 Clock control register (RCC CR) .89 7.4.2 Clock configuration register(RCC CFGR) 7.4.3 Clock interrupt register(RCC CIR) 7.4.4 APB peripheral reset register 2(RCC_ APB2RSTR) 96 7.4.5 APB peripheral reset register 1(RCC_ APB1RSTR) 98 7.4.6 AHB peripheral clock enable register(RCC_ AHBENR) 100 7.4.7 APB peripheral clock enable register 2 (RCC_ APB2ENR) .,.101 7.4.8 APB peripheral clock enable register 1(RCC APBlENR) .103 74. 9 RTC domain control register(RCC BDCR) 105 7. 4.10 Control/status register(RCC CSR) 7.4.11 AHB peripheral reset register(RCC_ AHBRSTR) 109 7.4.12 Clock configuration register 2(RCC_ CFGR2 .110 7.4.13 Clock configuration register 3(RCC_ CFGR3) 7. 4.14 Clock control register 2(RCC CR2) ·1 112 4/655 DoclD025023 Rev 1 / Contents 7.4.15 RCC register map General-purpose I/Os(GPIO) 115 8.1 PLo introduction 115 8.2 GPO main features 115 8.3 GPlO functional description ,,,,,,,,,,,,115 8.3.1 General-purpose I/O(GPIO) 117 8.3.2 l/0 pin alternate function multiplexer and mapping ....118 8.3. 3 10 port control registers ..118 8.3.4 1/o port data registers 119 8.3.5 1/o data bitwise handling 119 8.3.6 GPIO locking mechanism 119 8.3.7 10 alternate function input/output 120 8.3.8 External interrupt/wakeup lines 120 8.3.9 Input configuration 120 8.3.10 Output configuration 8.3. 11 Alternate function configuration 8.3.12 Analog configuration ,,,,122 8.3.13 Using the HSE or LSE oScillator pins as GPlOs 123 8.3.14 Using the GPIo pins in the rtC supply domain 8.4 GPIO registers 123 8.4.1 GPlO port mode register(GPlOx_ MODER)(x=A.F) .123 8.4.2 GPlo port output type register(GPIOX OTYPER)(X=A.F) 124 8.4.3 GPIO port output speed register(GPIOX OSPEEDR (x=A.F) 124 GPIO port pull-up/pull-down register(GPIOX PUPDR) (x=A.F 125 8.4.5 GPIO port input data register (GPlOX IDR)(X=A.F) 125 8.4.6 GPlO port output data register(GPIOX ODR)(x=A.F) 126 8.4.7 GPIO port bit set/reset register(GPIOX_ BSRR)(X=A.F) .126 8.4.8 GPlO port configuration lock register(GPIOX_LCKR) (X=A. B) 127 8.4.9 GPlO alternate function low register (GPlOX AFRL)(X=A,B)... 128 8. 4.10 GPlo alternate function high register(GPIOX AFRH) (X=A, B) 128 8.4.11 GPlo port bit reset register (GPIOX BRR)(X=A.F) 129 8.4.12 GPlO register map 130 DocID025023 Rev 1 5/655 Contents System configuration controller (SYSCFG) 132 9.1 SYSCFG registers 132 9.1.1 SYSCFG configuration register 1(SYSCFG CFGR1) .132 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG EXTICR1) 134 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG EXTICR2 134 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG EXTICR3)..... ,,,,,,,,,,,,,135 0.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG EXTICR4) ,,,,,,...136 9.1.6 SYSCFG configuration register 2(SYSCFG CFGR2) 137 9.1.7 SYSCFG register maps 138 10 Direct memory access controller(DMA)....∴………∴.139 10.1 DMA introduction 139 10.2 DMA main features 139 10.3 DMa functional description 140 10.3.1 DMA transactions 140 10.3.2 Arbiter ...141 10.3.3 DMA channels 10.3.4 Programmable data width, data alignment and endians .142 10.3.5Err nageme 144 10.3.6 Interrupts 144 10.3.7 DMA request mapping 145 ). 4 DMA register 147 10.4.1 DMA interrupt status register(DMA ISR) 147 10.4.2 DMA interrupt flag clear register(DMA IFCR) 148 10.4.3 DMA channel x configuration register(DMA_ CCRX)(x=1.5, where x channel number) 10.4.4 DMA channel x number of data register(DMA CNDTRX)(X=1.5 where x= channel number) .,,151 10.4.5 DMA channel x peripheral address register(DMA CPARx)(x=1.5. where x= channel number) 10.4.6 DMa channel x memory address register(DMA CMARX)(x=1.5, where x channel number 152 10.4.7 DMA register map 153 Interrupts and events 155 6/655 DoclD025023 Rev 1 / Contents 11.1 Nested vectored interrupt controller(NVIC) 155 11.1.1 NVIC main features 11.1.2 Sys Tick calibration value register 155 11.1.3 Interrupt and exception vectors 155 11.2 Extended interrupts and events controller (EXTI) 156 11.2.1 Main features ..157 11.2.2 Block diagram .,.,158 11.2.3 Event management .,,,158 11.2.4 Functional description 158 11.2.5 External and internal interrupt/event line mapping 160 11.3 EXTI registers 161 11.3.1 Interrupt mask register(EXTI IMR) ....16 11.3.2 Event mask register(EXTI EMR) 162 11.3.3 Rising trigger selection register(EXTI RTSR) 162 11.3.4 Falling trigger selection register(EXTI FTSR) 163 11.3.5 Software interrupt event register(EXTI SWIER) .163 11.3.6 Pending register(EXTI PR) 164 11.3.7 EXTI register map 165 12 Analog-to-digital converter(ADC) ■■■■■■■ 166 12.1 ntroduction 66 12.2 ADC main features 167 12.3 ADC pins and internal signals 168 12.4 ADC functional description ..169 12.4. Calibration(ADCAL 169 12.4.2 ADC on-off control (ADEN, ADDIS, ADRDY ,,,,,,,,,,,,,170 12.4.3 ADC clock(CKMODE) 171 12.4.4 Configuring the adc ..172 12.4.5 Channel selection (CHSEL, SCANDIR .172 12.4.6 Programmable sampling time(SMP) 12. 4.7 Single conversion mode (ConT=0) 12.4.8 Continuous conversion mode(cont=1) 174 12. 4.9 Starting conversions (ADSTART) .175 124.10Ti 175 12. 4.11 Stopping an ongoing conversion(ADSTP)........... 176 12.5 Conversion on external trigger and trigger polarity(EXTSEL, EXtEn). 177 DocID025023 Rev 1 7655 Contents 12.5.1 Discontinuous mode(DIScEn) 178 12.5.2 Programmable resolution(RES)-fast conversion mode 178 12.5.3 End of conversion, end of sampling phase(EOC, EoSMP flags) 179 12.5.4 End of conversion sequence(EOSEQ flag 180 12. 5.5 Example timing diagrams(single/continuous modes hardware/software triggers) 180 12.6 Data management 182 12.6. 1 Data register& data alignment(ADC DR, ALIGN) 182 12.6.2 ADC overrun(OVR, OVRMOD) 182 12.6.3 Managing a sequence of data converted without using the dma 183 12.6. 4 Managing converted data without using the DMA without overrun .. 183 12.6.5 Managing converted data using the DMA .,,,,,,,,,,,183 12.7 Low power features .184 12.7.1 Wait mode conversion 184 12.7.2 Auto-off mode (AUTOFF .185 12.8 Analog window watchdog(AWDEN, AWDSGL, AWDCH, AWD HTR/LTR, AWD) 186 12.9 Temperature sensor and internal reference voltage 187 12.10 ADC interrupts 190 12.11 ADC registers 19 12.11.1 ADC interrupt and status register(ADC_ ISR) .19 12.11.2 ADC interrupt enable register(ADC IER) .192 12.11.3 ADC control register(ADC CR) 193 12.11.4 ADC configuration register 1(ADC CFGR1 12.11.5 ADC configuration register 2(ADC CFGR2 .198 12.11.6 ADC sampling time register(ADC_ SMPR) 198 12.11.7 ADC watchdog threshold register(ADC_TR) 199 12.11.8 ADC channel selection register (ADC_ CHSELR) 200 12.11. 9 AdC data register(ADC DR) 12.11.10 ADC common configuration register(ADC_ CCR 201 12.11.11 ADC register map 202 13 Advanced- control timers(TIM1) 204 13.1 TiM1 introduction 204 13.2 TIM1 main features ,,204 13.3 TIM1 functional description 206 13.3.1 Time-base unit 206 8/655 Docl D025023 Rev 1 / Contents 13.3.2 Counter modes 208 13.3.3 Repetition counter 217 13.3.4 Clock sources∵… ..219 13.3.5 Capture/compare channels 222 13.3.6 Input capture mode ....225 13.3.7 PWM input mode 226 13.3.8 Forced output mode .227 13.3.9 Output compare mode 227 13.3.10 PWM mode 28 228 13.3.11 Complementary outputs and dead-time insertion 231 13.3. 12 Using the break function 233 13.3.13 Clearing the OCXREF signal on an external event 236 13.3. 14 6-step PWM generation ....238 13.3.15 One-pulse mode ..239 13.3.16 Encoder interface mode 240 13.3.17 Timer input XOR function 243 13.3.18 Interfacing with Hall sensors .243 13.3. 19 TIMX and external trigger synchronization 245 13.3.20 Timer synchronization 248 13.3.21 Debug mode ..248 13.4 TIM1 registers 249 13.4.1 TIM1 control register 1(TIM1_ CR1) 249 13.4.2 TIM1 control register 2(TIM1 CR2) 250 13.4.3 TIM1 slave mode control register (TIM1 SMCR 252 13. 4.4 TIM1 DMA/interrupt enable register(TIM1 DIER) 254 13.4.5 TIM1 status register (TIM1 SR) ....256 13.4.6 TIM1 event generation register (TIM1_ EGR ..257 13.4.7 TIM1 capture/compare mode register 1(TIM1 CCMR1)..... 259 13.4.8 TIM1 capture/compare mode register 2(TIM1 CCMR2)...... 262 13.4.9 TIM1 capture/compare enable register (TIM1 CCER) 13.4.10 TIM1 counter(TIM1 CNT 267 13. 4.11 TIM1 prescaler (TIM1_PSC) 267 13. 4.12 TIM1 auto-reload register (TIM1_ARR) 267 13.4.13 TIM1 repetition counter register (TIM1 RCR 268 13. 4.14 TIM1 capture/compare register 1(TIM1_CCR1) 268 13.4.15 TIM1 capture/compare register 2(TIM1 CCR2 269 13.4.16 TIM1 capture/compare register 3(TIM1 CCR3) 269 DocID025023 Rev 1 9/655 Contents 13.4.17 TIM1 capture/compare register 4(TIM1 CCR4) 270 13.4.18 TIM1 break and dead-time register (TIM1 BDTR) .270 13.4.19 TIM1 DMA control register(TIM1_DCR 272 13.4.20 TIM1 DMA address for full transfer (TIM1 DMAR) 273 13.4.21 TIM1 register map .274 14 General-purpose timers(TIM3 ,,.276 14.1 tiM3 introduction 276 14.2 tIM3 main features ,,,,,276 14.3 TIM3 functional description ··· 277 14.3.1 Time-base unit 277 143.2 Counter modes 279 143.3 Clock sources 288 14.3.4 Capture/compare channels ..,29 14.3.5 Input capture mode 292 14.3.6 PWM input mode 294 14.3.7 Forced output mode 295 4.3.8 Output compare mode 295 14.39 PWm mode 296 14.3.10 One-pulse mode 299 14.3.11 Clearing the OCXREF signal on an external event 300 143.12 Encoder interface mode 30 14.3.13 Timer input XoR function 303 14.3. 14 Timers and external trigger synchronization 304 14.3.15 Timer synchronization 307 14.3.16 Debug mode 312 14.4 tiM3 registers 14.4.1 TIM3 control register 1(TIM3 CR1) ...313 14.4.2 TIM3 control register 2(TIM3_ CR2 .,,315 14.4.3 TIM3 slave mode control register(TIM3 SMCR) 316 14.4. 4 TIM3 DMA/Interrupt enable register(TIM3 DIER) .318 14.4.5 TIM3 status register(TIM3 SR) 319 14.4.6 TIM3 event generation register (TIM3 EGR) 14.4.7 TIM3 capture/compare mode register 1(TIM3 CCMR1) 322 14.4.8 TIM3 capture/compare mode register 2 (TIM3 CCMR2) 325 14.4.9 TIM3 capture/compare enable register (TIM3_ CCER .326 14. 4.10 TIM3 counter(TIM3 CNT) .328 10655 DoclD025023 Rev 1 /

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试读 127P stm32f030参考手册
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再好一点儿 是官方STM32F030的参考手册,英文版,太贵了
2018-03-19
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baobo16321 是官方STM32F030的参考手册,英文版
2017-03-11
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huelion 学习了 写的很详细,
2016-05-14
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