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or modifications due to changes in technical specifications.

EN25Q32B

Rev. A

Issue Date: 2010

FEATURES

• Single power supply operation

- Full voltage range: 2.7-3.6 volt

• Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

• 32 M-bit Serial Flash

- 32 M-bit/4096 K-byte/16384 pages

- 256 bytes per programmable page

• Standard, Dual or Quad SPI

- Standard SPI: CLK, CS#, DI, DO, WP#

- Dual SPI: CLK, CS#, DQ

, DQ

, WP#

- Quad SPI: CLK, CS#, DQ

, DQ

• High performance

- 104MHz clock rate for one data bit

- 80MHz clock rate for two data bits

- 80MHz clock rate for four data bits

• Low power consumption

- 12 mA typical active current

- 1 μA typical power down current

• Uniform Sector Architecture:

- 1024 sectors of 4-Kbyte

- 64 blocks of 64-Kbyte

- Any sector or block can be erased individually

• Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

• High performance program/erase speed

- Page program time: 0.8ms typical

- Sector erase time: 50ms typical

- Block erase time 200ms typical

- Chip erase time: 15 seconds typical

• Lockable 512 byte OTP security sector

• Minimum 100K endurance cycle

• Package Options

- 8 pins SOP 200mil body width

- 8 contact VDFN

- 16 pins SOP 300mil body width

- 24 balls BGA (6x8mm)

- All Pb-free packages are RoHS compliant

• Industrial temperature Range

GENERAL DESCRIPTION

The EN25Q32B is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection

mechanisms. The EN25Q32B supports the standard Serial Peripheral Interface (SPI), and a high

performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ

(DI),

(DO), DQ

(WP#) and DQ

(NC). SPI clock frequencies of up to 80MHz are supported allowing

equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the

Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,

using the Page Program instruction.

The EN25Q32B is designed to allow either single

Sector/Block at a time or full chip erase operation. The

EN25Q32B can be configured to protect part of the memory as the software protected mode. The

device can sustain a minimum of 100K program/erase cycles on each sector

or block.

EN25Q32B

32 Me

abit Serial Flash Memor

with 4Kb

te Uniform Sector

or modifications due to changes in technical specifications.

EN25Q32B

Rev. A

Issue Date: 2010

Table 1. Pin Names

Symbol Pin Name

CLK

Serial Clock Input

DI (DQ

)

Serial Data Input (Data Input Output 0)

DO (DQ

)

Serial Data Output (Data Input Output 1)

CS#

Chip Enable

WP# (DQ

)

Write Protect (Data Input Output 2)

NC(DQ

)

Not Connect (Data Input Output 3)

Vcc

Supply Voltage (2.7-3.6V)

Vss

Ground

No Connect

Note:

1. DQ

and DQ

are used for Dual and Quad instructions.

2. DQ

~ DQ

are used for Quad instructions.

SIGNAL DESCRIPTION

Serial Data Input, Output and IOs (DI, DO and DQ

, DQ

)

The EN25Q32B support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions

use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the

rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to

read data or status from the device on the falling edge CLK.

Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or

data to the device on the rising edge of CLK and read data or status from the device on the falling edge

of CLK.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is

deselected and the Serial Data Output (DO, or DQ

, DQ

and DQ

) pins are at high impedance.

When deselected, the devices power consumption will be at standby levels unless an internal erase,

program or status register cycle is in progress. When CS# is brought low the device will be selected,

power consumption will increase to active levels and instructions can be written to and data read from

the device. After power-up, CS# must transition from high to low before a new instruction will be

accepted.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function

is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial

Data IO (DQ

) for Quad I/O operation.

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ZZT175

2015-04-18

有帮助，谢谢
xuzixin2

2015-01-05

讲的很详细非常好
stonebear7

2012-11-29

很詳細的資料~ 謝謝提供
kammy117

2011-09-13

时序讲解很详细的哦，谢谢啦~
jinfei_y

2013-12-15

很完整，谢谢提供！

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