nRF52840 数据手册

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The nRF52840 is designed around an ARM Cortex-M4 CPU with floating Point unit (FPU) and has 1MB flash with cache and 256kB RAM. As such it has the ability to support complex and demanding applications as a single chip solution. It offers a wealth of peripherals that include NFC, USB and multiple interface options including Quad SPI (QSPI). Security is paramount in today's IoT designs and the nRF52840 has high-end security features included to achieve best in clas security with an ARM CryptoCEll cryptographic system on chip and a full AES 128-bit encryption suite.
Feature list Applications: Advanced computer peripherals and I/ o de vices Internet of things(loT) Smart home sensors and controllers Keyboard Industrial lot sensors and controllers Multi-touch track Interactive entertainment devices Adyanced wearables Remote controls Health/ fitness sensor and monitor devices · Garning controllers Wireless payment enabled devices 4413417v1.0 NORD Contents Feature list 1 Revision history 12 2 about this document 13 2.1 Document naming and status 13 2.2 Peripheral naming and abbreviations 13 3 Register tables 14 2.3. 1 Fields and values 14 2. 4 Registers 14 2.4.1 DUMMY 14 3 Block diagram 16 4 Core components 18 4.1 CPU 18 4.1.1 Floating point interrupt 18 4.1.2 CPU and support module configuration 18 4.1.3 Electrical specification 4.2 Memory 19 4.2.1 RAM-Random access memory 20 4.2.2 Flash -Non-volatile memory 20 4.2.3 Memory map 20 4.2.4 Instantiation 22 4. 3 NVMC-Non-volatile memory controller 23 4.3.1 Writing to flash 4.3.2 Erasing a page in flash 24 4.3.3 Writing to user information configuration registers(UICR 24 4.3.4 Erasing user information configuration registers (UICR 24 4.3.5 Erase al 24 4.3.6 Access port protection behavior 24 4.3.7 Partial erase of a page in flash 4.3.8 Cache 25 4.3.9 Registers 4.3.10 Electrical specification 29 4.4 FICR- Factory information configuration registers 4.4.1 Registers 30 4.5 UICR- User information configuration registers 4.5.1 Registers 4.6 EasyDMA 45 4.6.1 EaSy DMA array list 4. 7 AHB multilayer 48 4. 8 Debug and trac 49 4.8.1 DAP-Debug access port 49 4.8.2 CTRL-AP-Control access port 50 4.8.3 Debug interface mode 52 4.8.4 Real-time debug 52 4.8.5 Trace 52 5 Power and clock management 54 4413417v1.0 NORD 5.1 Power management unit(PMU) 5.2 Current consumption 54 5.2.1 Electrical specification 5.3 POWER— Power supply 5.3.1 Main supply 50 5.3.2 USB supply 5.3.3 System OFF mode 5.3. 4 System on mode 57 5.3.5 RAM power control 57 5.3.6 Reset 58 5.3.7 Registers 59 5.3.8 Electrical specification 5.4 CLOCK- Clock control 5.4.1 HECLK controller 5. 4.2 LFCLK controller 82 5.4.3 Registers 84 4.4 Electrical specification 90 6 Peripherals 93 6.1 Peripheral intertace 93 6.1.1 Peripheral ID 93 6.1.2 Peripherals with shared ID 94 6.1.3 Peripheral registers 6.1.4 Bit set and clear 94 6.1.5 Tasks 94 6.1.6 Events 94 6.1.7 Shortcuts 6.1.8 Interrupts 95 6.2 AAR- Accelerated address resolver 96 6.2. 1 EaSyDMA 6.2.2 Resolving a resolvable address 96 6. 2. 3 Use case example for chaining radio packet reception with address resolution using aar. 97 6.2.4 IRK data structure 97 6.2.5 Registe 6.2.6 Electrical specification 100 6. 3 ACL Access control lists 100 6.3.1 Registers 102 6.4 CCM- AES CCM mode encryption 104 6. 4.1 Key-steam generation 104 6. 4.2 Encryption 105 6.4.3 Decryption 105 6.4.4 AES CCM and RADIO concurrent operation 6.4.5 Encrypting packets on-the-fly in radio transmit mode .106 6. 4.6 Decrypting packets on-the-fly in radio receive mode 107 6.4.7 CCM data structure 108 6. 4.& Easy DMA and ERROR event 109 6. 4.9 Registers 109 6.4.10 Electrical specification 5 COMP- Comparator 114 6.5.1 Differential mod 115 6.5.2 Single-ended mode 116 6.5.3 Registe 118 6.5.4 Electrical specification 124 6.6 CRYPTOCELL- ARM TrustZone Cryptocell 310 124 4413417v1.0 NORD 6.6.1 Usage 126 6.6.2 Always-on(AO) power domain 126 6.6.3 Lifecycle state(LCS 126 6.6.4 Cryptographic key sele 6.6.5 Direct memory access(DMA 127 6.6.6 Standards 127 6.6.7 Register 128 6.6. 8 Host interface 129 6. 7 ECB- AES electronic codebook mode encryption 132 6.7. 1 Shared resources 132 6.7.2 EaSy DMA 132 6.7.3 ecB data structure 132 6.7.4 Registers 133 6.7.5 Electrical specification 134 6. 8 EGU- Event generator unit .134 6.8.1 Registers 6.8.2 Electrical specification 41 6.9 GPIO- General purpose input/ output 141 6.9.1 Pin configuration 42 6.9.2 Registers 144 6.9.3 Electrical specification 148 6.10 GPIOTE- GPIo tasks and events 149 6.10.1 Pin events and tasks 6.10.2 Port event 6.10.3 Tasks and events pin contiguration 150 6.10.4 Registers 151 6.10.5 Electrical specification 155 6.11-s Inter-IC sound interface 155 6.11.1Mode 156 6.11.2 Transmitting and receiving 156 6. 11.3 Left right clock(LRCK 157 6. 11.4 Serial clock (SCK) 157 6. 11.5 Master clock(MCK 158 6. 11.6 Width, alignment and format 159 6.11./ Easy DMA 160 6.11.8 Module operation 6.11.9 Pin configuration 6.11.10 Registers 164 6.11.11 Electrical specification 172 6. 12 LP COMP- Low power comparator 173 6.12.1 Shared resources 174 6.12.2 Pin configuration 175 6.12.3 Registers 6. 12.4 Electrical specification 180 6.13 MWU Memory watch unit 180 6.13. 1 Registers 181 6. 14 NFCT- Near tield communication tag 196 6.14.1 Overvie 197 6.14.2 Operating states 199 6. 14.3 Pin configuration 200 6. 14.4 EaSyDMA 200 6.14.5 Frame assembler 201 6.14. 6 Frame disassembler 202 6. 14.7 Frame timing controller 203 4413417v1.0 NORD 6. 14.8 Collision resolution 6.14.9 Antenna interface 205 6.14. 10 NFCT antenna recommendations 205 6. 14.11 Battery protection 206 6. 14.12 References 206 6. 14.13 Registers 206 6. 14.14 Electrical specification 220 6. 15 PDM- Pulse density modulation interface 220 6.15.1 Master clock generator 221 6.15.2 Module operation 221 6.15.3 Decimation filter 222 6. 15. 4 EaSy DMA 222 6. 15.5 Hardware example 223 6. 15.6 Pin configuration 223 6. 15.7 Registers 224 6.15. 8 Electrical specification 6. 16 PPl- Programmable peripheral interconnect 230 6.16. 1 Pre-programmed channels 231 6.16.2 Register 232 6.17 PWM- Pulse width modu lation 6.17.1 Wave counter 236 6. 17.2 Decoder with EasyDMA 240 6.17.3 Limitations 247 6.17. 4 Pin configuration 247 6.17.5 Registers 248 6.18 QDEC - Quadrature decoder 255 6. 18. 1 Sampling and decoding 256 6.18.2 LED output 257 6.18. 3 Debounce fiters 257 6.18. 4 Accumulators 6.18.5 Output/input pins 258 6. 18.6 Pin configuration 6.18.7 Registers 259 6.18.8 Electrical specification 6. 19 QSPI-Quad serial peripheral interface 267 6. 19. 1 Configuring periphera 67 6.19.2 Write operation 6. 19.3 Read operation 6.19. 4 Erase operation 268 6.19.5 Execute in place 268 6. 19.6 Sending custom instructions 269 6. 19.7 Deep power-down mode 270 6.19.8 Instruction set 6. 19.9 Interface description 270 6.19.10 Registers 275 6. 19.11 Electrical specification 85 6.20 RADIO -2.4 GHz radio 285 6.20. 1 Packet configuratio 286 6. 20.2 Address configuration 287 6.20.3 Data whitening 288 6.20.4CRC 6.20.5 Radio states 289 6. 20.6 Transmit sequence 290 6.20. 7 Receive sequence 291 4413417v1.0 NORD 6.20. 8 Received signal strength indicator(RSSi) 293 6.20.9 Interframe spacing 293 6.20. 10 Device address match 294 6.20.11 Bit counter 294 6.20. IEEE 802.15.4 operation 295 6.20.13 EasyDMA 303 6.20. 14 Registers 304 6. 20.15 Electrical specification 325 6.21 RNG- Random number generator 330 6.21.1 Bias correction 331 6.21.2 Speed 331 6.21. 3 Registers 331 6.21.4 Electrical specification 333 6.22 RTC- Real-time counter 333 6.22. 1 Clock source 333 6. 22.2 Reso lution versus overflow and the prescaler 333 6.22.3 COUNTER register .334 6. 22.4 Overflow features 335 6.225 TICK event 335 6.22.6 Event control feature 335 6. 22.7 Compare feature 6.22.8 TASK and EVENT jitter/delay 338 6.22.9 Reading the CoUnter register 6.22.10 Registers 341 6. 22.11 Electrical specitication 346 6.23 SAADC- Successive approximation analog-to-digital converter 346 6.23.1 Input configuration 347 6.23.2 Reference voltage and gain settings 349 6.23. 3 Digital output 349 6.23. 4 EaSy DMA 349 6.23.5 Continuous sampling 351 6. 23.6 Oversampling 351 6. 23.7 Event monitoring using limits 6.23. 8 Calibration 6.23.9 Registers 352 6.23. 10 Electrical specification 366 6.24 SPl- Serial peripheral interface master 367 6. 24.1 Functional description 367 6. 24.2 Registers 370 6.24.3 Electrical specification 6. 25 SPIM- Serial peripheral interface master with Easy DMA 374 6.25.1 SPI master transaction sequence 375 6. 25.2 D/CX functionality 376 6.25.3 Pin configuration 377 6.25. 4 Easy DMA 6.25.5 Low power 378 6.25.6 Registers 379 6.25. 7 Electrical specification 388 6.26 SPIS Serial peripheral interface slave with EasyDMA 389 6.26.1 Shared resources 390 6.26.2 EaSyDMA 390 6.26.3 SPI slave operation 390 6. 4 Pin configuration 392 6.26.5 Registers 393 4413417v1.0 NORD 6.26.6 Electrical specification 402 6.27 SWI- Software interrupts 404 6.27.1 Registers 404 6.28 TEMP-Temperature sensor 404 6.28.1 Registers 405 6.28.2 Electrical specification 410 6.29 TWI-1-C compatible two-wire interface 410 6. 29. 1 Functional description 411 6. 29.2 Master mode pin configuration 411 6.293 Shared resources 412 6.29. 4 Master write sequence 412 6. 29.5 Master read sequence 413 6.29.6 Master repeated start sequence 413 6.29.7 Low power 414 6.29. 8 Registers 414 6. 29.9 Electrical specification 419 6.30 TIMER- Timer/counter 420 6. 30.1 Capture 421 6. 30.2 Compare 421 6. 30.3 Task delays 6.30. 4 Task priority 422 6. 30.5 Registers 422 6.31 TWIM-I-C compatible two-wire interface master with easy DMA 426 6. 31. 1 EaSyDMA 427 6. 31.2 Master write sequence 428 6.31.3 Master read sequence 428 6. 31.4 Master repeated start sequence 429 6.31.5 Low power 430 6.31.6 Master mode pin configuration 430 6. 31.7 Registers 431 6.31.8 Electrical specitication 439 6. 31.9 Pullup resistor 440 6.32 TWIS-12C compatible two-wire interface slave with EasyDMA 6. 32.1 EasyDMA 443 6. 32.2 TWI slave responding to a read command 443 6.32. 3 TWI slave responding to a write command .444 6. 32. 4 Master repeated start sequence 6. 32.5 Terminating an ongoing TWI transaction 6.32.6 Low power 6.32.7 Slave mode pin configuration 46 6.32. 8 Registers 447 6. 32.9 Electrical specification 454 6.33 UART Universal asynchronous receiver/transmitter 454 6.33.1 Functional description 455 6.33.2 Pin configuration 455 6.33 3 Shared resources 456 6.33. 4 Transmission 456 6.33.5 Reception 456 6.33.6 Suspending the UART 457 6.33. 7 Error conditions 457 6.33.8 Using the UART without flow control 457 6.33. 9 Parity configuration 6.33.10 Registers 6.33. 11 Electrical specification .464 4413417v1.0 NORD 6.34 UARTE -Universal asynchronous receiver/transmitter with Easy DMA 464 6.34.1 EaSyDMA 455 6. 34.2 transmission 465 6.34.3 Reception 456 6.34.4 Error conditions 468 6. 34.5 Using the UARTE without flow control 458 6. 34.6 Parity and stop bit configuration 468 6.34.7 Low power 468 6.34.8 Pin configuration 459 6.34.9 Registers 469 6. 34.10 Electrical specification 479 6.35 USBD- Universal serial bus device 479 6.35.1 uSB device states 480 6. 35.2 USB terminology 481 6.35. 3 USB pins 482 6. 35.4 USBD power-up sequence 482 6.35.5 USB pull-u 483 6.35.6 USB reset 483 6.35. 7 USB suspend and resume 484 6. 35.8 EaSy DMA .485 6.35.9 Control transfers 486 6. 35.10 Bulk and interrupt transactions 489 6.35.11 Isochronous transactions 492 6.35. 12 USB register access limitations 494 6.35.13 Registers 495 6.35. 14 Electrical specification 518 6.36 WDT- Watchdog timer 519 6.36. 1 Reload criteria 519 6. 36.2 Temporarily pausing the watchdog 520 6. 36. 3 Watchdog reset 520 6.36. 4 Registers 6.36.5 Electrical specification 523 7 Hardware and layout 524 7.1 Pin assignments 524 7.1.1 aQFN73 ball assignments 524 7.2 Mechanical specifications 527 7.2.1 aQFN73 7 mm package 527 7. 3 Reference circuitry 528 7.3.1 Circuit configuration no. 1 7.3.2 Circuit configuration no. 2 531 7.3.3 Circuit configuration no. 3 533 7.3.4 Circuit configuration no 4 7.3.5 Circuit configuration no 5 537 7.3.6 Circuit configuration no 6 7.3./ PCB guidelines 541 7.3. 8 PCB layout example 8 Recommended operating conditions 544 9 absolute maximum ratings 545 10 Ordering information 546 4413417v1.0 NORD

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