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Engineer-to-Engineer Note EE-240

Technical notes on using Analog Devices DSPs, Processors and development tools

Contact our technical support at dsp.support@analog.com and at dsptools.support@analog.com

Or visit our on-line resources http://www.analog.com/ee-notes and http://www.analog.com/Processors

ADSP-BF533 Blackfin® Booting Process

Contributed by Hiren Desai Rev 1 – June 3, 2004

customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property

Introduction

This EE-Note describes the booting process for the ADSP-BF531, ADSP-BF532, and ADSP-BF533

Blackfin

processors. Differences between silicon revision levels are noted.

This EE-Note discusses:

! Boot modes

! Loader file header information

! Initialization code

! Multi-application (multi-DXE) management

The Booting Process

Booting is the process of loading application code/data, stored in an external memory device (or external

host), into the various internal and external memories of the Blackfin processor. This is handled by the on-

chip boot ROM which is located in Blackfin memory at address

0xEF00 0000 to 0xEF00 03FF. Figure 1

shows the sequence of operations taken from source code to the final target stand-alone system.

Figure 1. ADSP-BF531/BF532/BF533 Stand-Alone System

ADSP-BF53x

Processor

Booting

Upon

RESET

Target System

External

Memory

Assembler and/or

Compiler

Linker

Loader

Source Files

.ASM, .C, .CPP

.DXE(s)

.DOJ(s)

.LDR

of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however

no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.

Boot Modes (Silicon Revision 0.3)*

Blackfin processors can boot from a flash/PROM via asynchronous Bank 0 of the EBIU or an SPI device

(memory or host) via the SPI interface. Table 1 lists ADSP-BF531/BF532/BF533 processor booting

modes, which are selected by the state of the BMODE[1:0] pins when the

RESET signal is de-asserted.

BMODE[1:0] Description (See Also Specific Blackfin Boot Modes on page 10

00 Executes from external 16-bit memory connected to ASYNC Bank0 (bypass boot ROM)

01 Boots from 8/16-bit flash/PROM

10 Boots from a SPI host in SPI Slave mode

11 Boots from a 8/16/24-bit addressable SPI memory in SPI Master mode with support for

Atmel AT45DB041B, AT45DB081B, and AT45DB161B DataFlash® devices

Table 1. Blackfin ADSP-BF531/BF532/BF533 Booting Modes

* For boot modes supported on previous revisions of silicon, refer to the

Appendix: Boot Modes vs. Silicon Revisions.

As Figure 1 illustrates, the loader utility (elfloader.exe) parses the input executable file (.DXE) and

creates a loader file (

.LDR)*, consisting of blocks preceded by headers. This loader file is then

programmed/burned into the external memory/device. The headers are read and parsed by the on-chip

boot ROM during booting.

* Refer to the VisualDSP++ 3.5 Loader Manual for 16-Bit Processors [1] for information on switches loader files

Loader File is programmed/burned into the External Memory/Device

ADSP-BF531/BF532/BF533 Processor

Figure 2. ADSP-BF531/BF532/BF533 Boot Process

Booting into scratchpad memory (0xFFB0 0000 – 0xFFB0 0FFF) is not supported. If booting to

scratchpad memory is attempted, the processor will hang within the on-chip boot ROM.

10-B

te Header for Block 2

10-B

te Header for Block 3

Block 2

Block 3

10-B

te Header for Block n

Block n

……………..

Loader File

10-B

te Header for Block 1

Block 1

L1 Memory

0xEF00 0000

...........

Flash/PROM or SPI

10-Byte Header for Block 1

Block 1

Block 2

10-Byte Header for Block 2

Block 3

App.

Code/

Data

Block 3

10-Byte Header for Block 3

10-Byte Header for ock n Bl

Block n

On-Chip Boot

ROM

SDRAM

Block 2

ADSP-BF533 Blackfin® Booting Process (EE-240) Page 2 of 28

The FLAG bits include:

" Bit 0: ZEROFILL - Indicates that the block is a buffer with zeros. ZEROFILL blocks have no

payload data. They simply instruct the on-chip boot ROM to zero COUNT bytes starting from

ADDRESS in memory. This yields a condensed loader file for applications with large zero buffers.

It is also very helpful for ANSI-C compliant projects which often require large buffers to be

zeroed during boot time.

" Bit 1: RESVECT – Indicates the reset vector after booting. All ADSP-BF531/BF532/BF533

derivatives use the same boot ROM. This bit is set to 0 for the ADSP-BF531/BF532 and it is set to

1 for the ADSP-BF533. After booting is complete, the on-chip boot ROM uses this bit to jump to

address

0xFFA0 0000 for the ADSP-BF533 or to address 0xFFA0 8000 for the ADSP-

BF531/BF532.

After a hardware reset, the reset vector (stored in the EVT1 register) is set to 0xFFA0 0000

or 0xFFA0 8000, depending on the RESVECT bit. If bit 4 (No Boot on Software Reset) of

the SYSCR register is set and a software reset is issued, the processor will vector to the

address set in the

EVT1 register. This reset vector can be reconfigured to another address

during runtime and hence, an application can vector to an address other than 0

xFFA0 0000

0xFFA0 8000 after a software reset. If the reset vector is modified during runtime,

ensure that the reset vector address within the EVT1 register is a valid instruction address.

This address can be internal instruction memory, SDRAM memory, or asynchronous

memory. The

EVT1 register does not have a default value. The value within this register

will be retained after a reset is issued. When BMODE = 00, the on-chip boot ROM is

bypassed and you must initialize the

EVT1 register before issuing a software reset.

" Bit 3: INIT – An initialization block (Init Block) is a block of code that executes before the actual

application code boots over it. When the on-chip boot ROM detects an Init Block, it boots the

block into internal memory and makes a CALL to it (initialization code must have an

RTS at the

end). After the initialization code is executed, it is typically overwritten with application code. See

Figure 5.

" Bit 4: IGNORE – Indicates a block that is not booted into memory. It instructs the boot ROM to

skip COUNT bytes of the boot stream. In master boot modes, the boot ROM can just modify its

source address pointer. In slave boot modes, the boot ROM must actively trash the payload data.

The current VisualDSP++® tools support IGNORE blocks for global headers only (currently the

4-byte DXE Count, see Multi-Application (Multi-DXE) Management section below).

" Bits 8:5: PFLAG - These bits are used for SPI Slave mode boot (BMODE = 10). PFLAG

indicates the

PF number used for the feedback strobe from the Blackfin processor to the Master

SPI host. This value can be between 1 – 15 (

0x1 – 0xF) for ADSP-BF531/BF532/BF533

processors. Refer to the SPI Slave Mode Boot via Master Host (BMODE = 10) section below for

further information on the usage of this PF strobe.

" Bit 15: FINAL – Indicates boot process is complete after this block. After processing a FINAL

block, the on-chip boot ROM jumps to the reset vector address stored in the

EVT1 register. The

processor is still in Supervisor mode and in the lowest priority interrupt (

IVG15) when it jumps to

L1 memory for code execution.

ADSP-BF533 Blackfin® Booting Process (EE-240) Page 4 of 28

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