单片机MCU外文文献

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ZHANG et ai. DEPENDENCE OF CELL DISTANCE AND WELL-CONTACT DENSITY ON MCU RATES 1585 0.4 First part 3.0um 5.0 um 301 T1 m 02 20 Second part 0 0.2 0.6 D [uI ime[ns Fig. 7. Threshold charge of LO and LI when the redundant latches are simul 0.4 taneously nipped. D is 0.5, 3.0, 0.5 um 3.0 um 二 5.0 um magnitude of threshold charge becomes bigger when D is in creased. As n is increased, charge sharing between LO and 0.2 becomes weaker as shown in Fig. 5. Charge is mainly collected slopes are deceasing into Ll by the bipolar effect. However, it becomes harder to el- evate the well potential under Ll because the latch Ll is placed 0.1 far away from LO(D>0.3 um). Thus, LET of the ion par ticle which simultaneously flips the redundant latches becomes higher Threshold charge are increased in lo and li by in 0.2 0.6 creasing D. Note that just the collected charge of tristate inverter Time[] TO and TI is shown in Fig. 7. Larger amount of charge is collected into inverter I0 and Il. Thus, the charge of Tl is larger Fig. 5. Transient drain current of To (a)and TI(b) caused by a particle hit at to than to when d is 0.5 um. But it does not influence the results when the redundant latches are simultancously flipped. D is 0.5, 3.0, 5.0 um. of the device simulations (a)Drain current waveform of To (b) Drain current waveform of T1 C. Contribution of well-contact Position to Suppress MCU 0.5u 3.0 order to analyze the relationship between well-contact po 5.0 0.8 sition and mcu tolerance, we place the well contacts adjacent s06}---1 to latches, DwC is shorten to 1.0 um from 20 um. LEt of the ion particle are 10 and 20 Mev. cm/ mg the redundant d0.4 0.5un 3.0 uTN 5.0un latches are aligned vertically(D=0.3 um) in these simula 0.2 tions. The volume of collected charge of lo and li are shown Fig. 8. When the di from 20 um to Voltage output 1.0 um, the magnitude of collected charge of the redundant Well potentia|一 latches Lo and ll decreases by 50%. It is because the well po 0.2 0.4 C6 08 tential under latches keeps steady by placing well contacts close Time [ns] to the latches. Bipolar effect under Lo and Ll is suppressed Fig. 6. Voltage outputs of inverter 10 of latch LO and the well potential under Thus, less charge is collected into the redundant latches the latch LO after a particle. D is 0.5, 3.0, 5.0 um Fig 9 shows the threshold charge of Lo influenced by Dwc when redundant latches are simultaneously flipped. D is 1.0, 2.0 and 3.0 um. The threshold charge exponentially decreases by in- Fig. 6 shows the voltage waveforms of inverter 10 of latch Lo creasing Dwc. There is a large amount of charge collected into and the well potential under Lo after a particle hit on the tris- the latch Lo when redundant latches are simultaneously Nipped tate inverter To D is 0.5, 3.0 and 5.0 um. The voltage wave- if the well contacts are placed adjacent to redundant latches. It forms keep low when the well potential is higher than 0.6 V. is because the adjacent well contacts stabilize the well potential The voltage waveforms start to go up when well potential de- The bipolar effect is also suppressed. Higher LET ion particle creases below 0.6 V. The flipped voltage waveforms cross the can are simultaneously flipped the redundant latches. Therefore, well potential waveforms at 0.6V. It is because the parasitic mcu tolerance of the redundant latches become stronger by bipolar transistor of latch LO can not turn off until the well po- shortened DwC tential decreases below 0.6 V When the well contacts are placed between the redundant ig. 7 shows the minimum magnitude of critical charge of latches LO and Ll as shown in Fig. 10, the magnitude of col the latches LO and LI when the redundant latches are simulta- lected charge is shown in Fig. ll. the collected charge of lo neously flipped. We call this charge as threshold charge The and ll decreases by about 60% and 90% respectively compared 1586 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL 61, NO. 4, AUGUST 2014 TO T1 T1∞z 2品5 DwC 10 20um DwC DWC LET [Mev-cm/mg T[MeV-cm" /mg] Fig8. Collected charge of the redundant latches LO and LI intluenced by tween the redundant latches o and Li when the well contacts are placed be Fig. 11. Collected charge of DwC. LET is 10 and 20 MeV. (Ill/ing TABLE I PARAMETERS FOR SER ESTIMATION F(ncm-s-)5.65×10 D=1.0 um x D=2.0um+ Qs (fC) 5.72 D=30 um D. So/l Error Rule Calculalion Eq (1[14 is used to calculate Ser in FIT (Failure In Time number of errors/109 hours) X NsER( Qcrit=F×A× Kx exp crit Dwc lumI Fig 9. Threshold charge ofLo by increasing Dwc when redundant latches are here f is the high-energy neutron flux and a is the drain area simultaneously flipped of transistors related to soft errors. K is a fitting parameter. Q s is called"charge collection efficiency that strongly depends on doping and supply voltage [15]. We use the parameter values as in Table I we use a fitting line to scaled Q s based on the Qs of 350 nm and 100 nm as [14] to 65 nm O MCU rate is calculated by the threshold(minimum) charge Particle hit of latch Lo at which the redundant latches are simultaneously flipped. Dwc is the distance between the redundant latches and well contacts as in Fig. 2. The distances between redundant 0.3m[凶凶囟区 latches D which we use for device simulations are shown in Table Il Dwc is 20 um. The threshold charge Qcrit and the ra PWELLI tios of mcu to sEU are also shown in Table ll. Fig 12 shows the ratio of mcu to SEU influenced by D on redundant latches from device simulations when Dwc is 20 um. Note that the ratio of mcu to seu which is lower than 0. 1% are not shown on Fig. 12. According to the device-simulation results as shown Fig. 10. The layout struclure in which well contacts are placed laced belween lhe in Table ll, the ratio of mcu to SEU exponentially decreases edundant latches by increasing D. If the well contacts are placed between re dundant latches, they are simultaneously flipped when Let is to the collected charge when Dwc is 20 um, even if the redun 35 Mev. cm2/mg, and the threshold charge is 45.7fC.The ratio of mcu to seu decreases to 0.073 dant latches are aligned vertically. In this case, generated charge under the latch lo can not cross over the well contacts to the ll side. Thus the charge sharing between the redundant latches is IIL. IMPACT OF CELL DISTANCE AND WELL-CONTACT DENSITY almost prevented. Also the bipolar effect is suppressed effec- ON REDUNDANT FES BY NEUTRON EXPERIMENTS tively, because the well contacts between the redundant latches The experimental results of neutron-induced MCU on D-FFs suppress the well potential elevation are described in this section. We use four different shift registers ZHANG et ai. DEPENDENCE OF CELL DISTANCE AND WELL-CONTACT DENSITY ON MCU RATES 1587 TABLE II QCRIT AND THE RATIO OF MCU TO SEU BY DEVICE SIMULATIONS WHEN Dwc IS 20 FFFF FF FFF-F器 凶区区 彐 凶区区区 d Qcrit MCU/SEU [% 0.58.31 50.18 0.69.95 37.70 1.011.3 29.70 10k FFs 1.517.2 10.59 i shift re 2.026.9 2.5309 0.97 3.0324 0.74 4.0515 0.026 区区区区区区区区区区区区区区囚DD 4.561.5 0.0046 FF「F-F閔FF[F 5.0754 00004 区区区区区区区区区区区区区wSS Fig10457 0073 引扫…彐 区区区区四区四区区区区区区区 50m 100 Fig. 13. Chip micrograph and conceptual layout structures of four different shift registers on the test chip 1um (b) 2um (c) s:26μm 3.6 um M:0.50m 13m Slave latch: Master latch 0.3 um Distance between Latches(D) [um Fig. 14. Distance bctwccn master or slave latches on shift register(a-(c) Fig 12. The ratio of mcu to SEU by increasing D when Dwc 20 um to estimate soft error rates on redundant fip-flops [13]. The de- pendence of MCU rates on the distance of FFs and well-contact density is also shown in this section 17.8 A. Test Chips 15 139 In order to measure the soft error rates we fabricated a 6.5 nm 10 bulk CMOs test chip as shown in Fig 13. Four different shift registers. Each shift register includes 10k FFs. All shift regis ters are constructed by ffs and clock buffer chain [16 These FFs are constructed in the same layout structure except for well D=0.5 um D=0. 66 um D=1.3 um D=0. 66 um contacts. The distance between the two rows in registers(a)-(c) Shift registers and the min distances between latch are 0 um, 1 um, and 2 um as shown in Fig. 13. These shift reg isters are used to estimate the cell-distance independence mcu Fig. 15. The ratio of MCU/set according to the min disatance between rates. Fig. 14 shows different distances between slave latches latches by experiments and between master latches according to flip-flop placements The well contacts of the shift registers(a-c)are inserted every 50 um. In order to obtain dependence of MCU rates on engineering LSI tester to control DUTs and collect shifted error well-contact density we fabricated well-contact arrays under data. Fig. 15 shows the ratio of mcu to sEU according to the the power and ground tap of the shift register(d)as shown in minimum distance by experiments. The ratio of mcu to sEU Fig 13. The well-contact density is 60x higher than the others. is reduced from 17.87 to 0.2%o by inserting well-contact ar rays under supply and ground rails of FFs, even if the minimum B. Experimental results analysi distance is the same. Therefore, we can improve soft-error re silience of the redundant FFs by increasing well contacts be The spallation neutron irradiation experiments were carried tween redundant latches. It also shows that in the fabricated out at RCNP. In order to increase error counts, 28 chips is mea- technology, almost all MCU is caused by the parasitic bipolar sured at the same time using stacked dut boards. We use an effect since it is caused by well-potential perturbation [17] 1588 IEEE TRANSACTIONS ON NUCLEAR SCIENCE. VOL 61. NO. 4. AUGUST 2014 TABLE III 00 THE RATIO OF MCU TO SEU INFLUENCED BY DwC ACCRODING TO THE DEVICE SIMULATIONS 2.07 Dwc LumI D27550010.015020.0250 MCU/SEU [%] 0.5 4.5726.2843.6346.3848.794965 0.6 2.3122.3128.1833.5637.704574 u0O 100004288920.5727.6929703663 1.5 0427089.3710.591352 2.0 0200.571.601.94384 045 0.51 0.97 57 30 0.20.74 4.0 -0.00170.0260.32 0.3 4.5 00046002 Distance between Latches(D)[um 5.0 -00038 Fig. 17. Distance-dependence of the ratio ofmcu to seu by device simula tions 100 100 1.67 DwC=25.0um o DWc=200um■ DWc=150um口 0.0}Dw=10um米 DWC=5.00um DwC=2. 75um x 0.001 03 Distance betw/een Latches(D)[um 0. 0.3 Fig. 16. Distance-dependence of the ratio of mcu to seU by device-simula Distance between Latches(D)[um tions in different Dwc Fig. 18. Distance-dependence of the ratio of mcu to seu by neutron experi Intends IV. COMPARISON OF DEVICE-LEVEL SIMULATION RESULTS AND EXPERIMENTAL RESULTS distributed along the same straight line. Therefore, the MCU i FFs are placed every 5 um on the measured chips. In order to seu does not depend on the drive strength and load capacitance get device-simulation result with higher accuracy, we use dif- It is obviously shown that the ratios ofmcu to seu by device ferent(Dwc)as shown in Table Ill for calculating the ratio simulations and experimental results exponentially decrease by of mcu to sEu. Note that the ratios of mcu to seu below increasing the cell distance D. The fitting line exponentially de 0.001%are not shown in the table. The distance-dependence of creases influenced by D-2.07 by device simulations. note that MCU /sEU by device simulations are shown in Fig. 16. Even the fitting line is over 100%, it is means the ratio of MCU/SEU if the ratios of mcu to seu are different when we use different is 100% when D is shorter than 0.3 um. According to the results Dwc in device-simulations, all of the ratios decrease as shown of experiments and simulations, we must implement redundant in F1g 16 FFs whose latches are separated by 4 um from each other, in We assume average values of all mcu/ seu for different order to achieve 100x higher soft-error tolerance in redundant Dwc in Table Ill from device-simulations is the MCU/SEU FFs than in non-redundant FF. It consumes huge area or compli- rate at each D. The average ratios of mcu to seu are shown in cated design procedures and these drawbacks become dominant Fig 17. Fig. 1& shows the distance-dependence of MCU seu by the process scaling on FFs which is obtained from the shift registers(a)-(). The Only one MCU is observed when the well contacts are ratio of mcu to seu (y-axis) is obtained from measurement placed between flip-flops by neutron experiments. Thus, MCU results. The ratio of McU to SeU exponentially decreases influ- is suppressed by placing well-contact array under the supply enced by D (D is the distance between redundant latches) and ground rail. However, the well potential is fixed in this and fitting line shows that it is almost 100% when n< 0. 3 m. layout structure. This kind of structure can not be used if the The master and slave latches in the FF have different structures. well potential is changed to mitigate variations or to contro However, the ratio of mcu to seU by neutron experiments is performance and leakage ZHANG et ai. DEPENDENCE OF CELL DISTANCE AND WELL-CONTACT DENSITY ON MCU RATES 1589 There is only heavy ion model which is used in the device [4]G. Gasiot, D. Giot, and P. Roche, " Multiple cell upsets as the key simulations. Mostly, it is difficult to compare the results between contribution to the total ser of 65 nm CMOS SRAMS and its depen device-Simulations and neutron experiments we examined de dence on well engineering, IEEE Trans. Nucl. Sci., vol 54, no 6, pp 2468-2473,Dec.2007 vice-Simulations agree with the conditions of neutron experi- [5 T. Uemura, Y. Tosaka, H. Matsuyama, K. Shono, C. Uchibori, K ments as possible as we can. The device-simulation results co- Takahisa. M. Fukuda. and K. hatanaka. " SEILA: Soft crror immunc incide with the experimental results very well in this work. We latch for mitigating multi- node-SEU and local-clock-SET, " in Proc Int. Rel. Phys. Symp., May 2010, pp 218-223 reveal that the mCu/seu rates can be calculated by simple [6 D. Krueger, E Francon, and J. Langsdorf, "Circuit design for voltage device-simulations scaling and ser immunity on a quad-core itanium processor, in Proc IEEE Int. Solid-State Circuits Con., Feb. 2008, pp 94-95 [7]K. Zhang, R. Yamamoto, J Furuta, K. Kobayashi, and H. Onodera, V. cONCLUSION "Parasitic bipolar effects on soft errors to prevent simultaneous fips of redundant fip-flops, " in Proc. Int. Rel. Phys. Symp., Apr. 2012, pp Based on the results of device simulations we show that 5B.2.1-5B.2.4. charge sharing and bipolar effect are two main factors when [8 N. Atkinson, A. Witulski, W. Holman, J. Ahlbin, B. Bhuva, and L Massengill, "Layout technique for single-event transient mitigation via MCU occur in redundant latches. MCU is suppressed when the pulse quenching IEEE Trans. Nucl. Sci., vol. 58, no 3, pp. 885-890 distance between the redundant latches(D)is increased. Total collected charge of Lo and li decreases by 50% by placing [9 J. Black, A. Stcrnbcrg, M. Allcs, A. Witulski. B. Bhuva, L Massengill, I. Benedetto, M. Baze, I. Wert, and M. Hubert, ""HBD layout isola the well contacts adjacent to the redundant latches at which the tion techniques for multiple node charge collection mitigation, IEEE distance between well contacts and redundant latches Dwc is Trans. Nucl. Sci., vol. 52, no. 6, pp. 2536 2541, Dec. 2005 1.0 um. Total collected charge of Ll reduces by 90% when the [Io O. A. Amusan, A. F. Witulsk1, L. w. Massengill, B. L. Bhuva, PR well contacts are placed between redundant latches. The ratio of Fleming, M. L. Alles, A.L. Sternberg, J. D. Black, andR. D. Schrimpf, Charge collection and charge sharing in a 130 nm CMOS technology, MCu to seu decreases to 0.073% in this kind of layout struc IEEE Trans. Nuc/. Sci., vol 53, no 6, pp. 3253-3258, Dec 2006 ture. according to the results of neutron experiments and de- [11] D Hansen, E. Miller, A. Kleinosowski, K. Kohnen, A Le, D. Wong, vice simulations, the ratio of mcu to seu exponentially de K. Amador, M. Baze, D. De Salvo, M. Dooley, K. Gerst, B. Hughlock B Jeppson, R. Jobe, D. Nardi, I. Ojalvo, B. Rasmussen, D. Sunder creases by increasing the distance of latches D. The fitting lines land, J. Truong, M. Yoo, and E. Zayas, Clock, fip-flop, and combi are influenced by D-1.67 and D-2.7 by experiments and simu- natorial logic contributions to the seu cross section in 90 nm asic lations respectively. Experimental results also show that mCu technology, IEEE Trans. Nucl Sci., vol. 56, no. 6, pp. 3542-3350 Dcc.2009 rates drastically reduce by inserting well-contact arrays under [12]K. Zhang and K. Kobayashi, "Contributions of charge sharing and supply and ground rails. The number of mcU reduces to one bipolar effects to cause or suppress MCUs on redundant latches, "in Proc. Int. Rel. Phys. Symp., Apr 2013, pp. SE. 5.1 SE.5. 4 We use several simple device simulations to estimate the mCU [3J. Furuta, K. Kobayashi, and H Onodera. "Impact of cell distance and tolerance of redundant latches the results of device simulations well-conlact densily un neutronl-induced muliple cell upsets, in Proc almost coincides with the neutron experiments. Int. Rel. Phys. Symp., Apr. 2013, pp. 6C.3. 1-6C3 4 [14] P. Hazucha and C svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Trans. Nuc/. Sci., vol REFERENCES 47,no.6,pp.2586-2594,Dec.2000 [15] P. Hazucha, C Svensson, and s. Wender, Cosmic-ray soft error rate [1]S. Mitra, M. Zhang, S. Waqas. N. Scifcrt, B. Gill, and K Kim, Com naracterization of a standard 0. 6 um CMOS process, "IEEE J. Solid binational logic soft error correction, in Proc. IEEE International Test State Circuits., vol. 35, no. 10, pp. 1422-1429, 2000 Conf, Oct 2006, pp. 1-9 [16 J Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera, Measur [2]D. Krueger, E. Francom, and J. Langsdorf, "Circuit design for voltage mcnt of ncutron-induced SET pulsc width using propagation-induccd scaling and sEr immunity on a quad-core itanium processor, Proc pulse shrinking, in Prac. Int. Rel. Phys. Symp., Apr. 2011, pp Int. Solid-State Circuits Con/., pp 94-95, Feb. 2008 5B.2.1-5B.2.5 3] B. Olson, D Ball, K. Warren, L Massengill, N. Haddad, S. Doyle, and [17] T Nakauchi, N. Mikami, A. Oyama, H Kobayashi, H. Usui, and J D McMorrow, "Simultaneous single event charge sharing and para Kase, A novel technique for mitigating neutron-induced multi-cell sitic bipolar conduction in a highly-Scaled SRAMdesign, "IEEE Trans upset by means ofback bias, "in Proc: In. Rel. Phys. Symp., May 2008, Nucl. Sci., vol. 52, no. 6, pp. 2132-2136, Dec 2005 pp.187-191

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