LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY eda1 IS
PORT ( CLK:IN STD_LOGIC;
C_OUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
L0,L1,L2,L3,L4,L5:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE BHV OF eda1 IS
SIGNAL Q:INTEGER RANGE 0 TO 50000000;
SIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL CLK2:STD_LOGIC;
SIGNAL S1:STD_LOGIC;
SIGNAL S10:STD_LOGIC;
SIGNAL m1:STD_LOGIC;
SIGNAL m10:STD_LOGIC;
SIGNAL h1:STD_LOGIC;
SIGNAL h10:STD_LOGIC;
SIGNAL SEC1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEC10:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL MIN1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL MIN10: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HOUR1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HOUR10: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF Q=50000000 THEN CLK2<='1';Q<=0;
ELSE CLK2<='0';Q<=Q+1; END IF;
END IF;
END PROCESS;
PROCESS(CLK2)
BEGIN
IF CLK2'EVENT AND CLK2='1' THEN
IF SEC1<"1001" THEN SEC1<=SEC1+1;S1<='0';
ELSE SEC1<="0000";S1<='1';
END IF;
END IF;
END PROCESS;
PROCESS(S1)
BEGIN
IF CLK2'EVENT AND CLK2='1' THEN
IF S1='1' THEN
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