驱动12864lcd液晶VHDL程序

附件ＶＨＤＬ源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LCD IS
  PORT(
 CLK: IN STD_LOGIC;
 X1,X2,X3:IN INTEGER RANGE 1 TO 9;
 RS,RW,CS1,CS2,E:OUT STD_LOGIC;
 Q: BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)
 );
END LCD; 
ARCHITECTURE BEHAV OF LCD IS
 TYPE STATES IS (ST0, ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST8,ST9,ST10,ST11,ST12,ST13,ST14,ST15,ST16,ST17,ST18,ST19,ST20);
 SIGNAL PRE_STATE,NEXT_STATE:STATES ;
 TYPE SHUZU IS ARRAY   (0 TO 1023)  OF STD_LOGIC_VECTOR(7 DOWNTO 0);
 SIGNAL DATA :SHUZU :=(…………）；
 BEGIN
   CLOCK:PROCESS(CLK)                                                      --将时钟进行分频
   VARIABLE CONT: INTEGER RANGE 0 TO 20;
      BEGIN 
             IF CLK'EVENT AND CLK='1' THEN
                CONT:=CONT+1;
                IF CONT = 12 THEN DATALOCK<='0';CONT:=0;
                ELSIF CONT=9 THEN DATALOCK<='1';
                END IF;
             END IF;
  END PROCESS CLOCK;
  EN<= NOT DATALOCK;