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TJA1101B

100BASE-T1 PHY for automotive Ethernet

Rev. 1 — 1 March 2021 Product data sheet

1 General description

The TJA1101B is a 100BASE-T1-compliant Ethernet PHY optimized for automotive use

cases such as gateways, IP camera links, radar modules, driver assistance systems and

back-bone networks. The device provides 100 Mbit/s transmit and receive capability over

a single unshielded twisted-pair cable, supporting a cable length of up to at least 15 m.

The TJA1101B has been designed for automotive robustness and ISO 26262, ASIL-A

compliance, while minimizing power consumption and system costs.

Being ASIL-A compliant, adequate safety features have been implemented to ensure that

ASIL requirements are met at system level. Additional documentation, including a safety

manual, is available on request.

The TJA1101B supports OPEN Alliance TC-10-compliant sleep and wake-up request

forwarding, with an always-on power domain connected directly to the battery supply

without the need for a dedicated voltage regulator.

2 Features and benefits

2.1 General

• 100BASE-T1 PHY

• MII- and RMII-compliant interfaces

• Compact 36-pin HVQFN package (6 × 6 mm) for PCB space-constrained applications

• ISO 26262, ASIL-A compliant

2.2 Optimized for automotive use cases

• Transmitter optimized for capacitive coupling to unshielded twisted-pair cable

• Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m

• Enhanced integrated PAM-3 pulse shaping for low RF emissions

• EMC-optimized output driver strength for MII and RMII

• MDI pins meet class IV conducted emission limit as per OPEN Alliance EMC

Specification 2.0

• MDI pins protected against ESD to ±6 kV HBM and ±8 kV IEC61000-4-2

• MDI pins protected against transients in automotive environment

• MDI pins do not need external filtering or ESD protection

• Automotive-grade temperature range from -40 °C to +125 °C

• Automotive product qualification in accordance with AEC-Q100

• Host-configurable MDI polarity

• Automated polarity detection and correction

NXP Semiconductors

TJA1101B

100BASE-T1 PHY for automotive Ethernet

Symbol Pin Type

[1]

Description

DDA(TX)

[2]

11 P 3.3 V analog supply voltage for the transmitter

TRX_P 12 AIO + terminal for transmit/receive signal

TRX_M 13 AIO - terminal for transmit/receive signal

DDA(TX)

[2]

14 P 3.3 V analog supply voltage for the transmitter

DDD(3V3)

15 P 3.3 V digital supply voltage

DDD(1V8)

16 P 1.8 V digital supply voltage (internally or externally generated; needs to be filtered if

generated internally)

RXER 17 O MII/RMII receive error output

CONFIG3 17 I pin strapping configuration input 3

TXCLK 17 O transmit clock output in test mode and during slave jitter test

RXDV 18 O MII receive data valid output

CONFIG2 18 I pin strapping configuration input 2

CRSDV 18 O RMII mode: carrier sense/receive data valid output

DD(IO)

[3]

19 P 3.3 V I/O supply voltage

CLK_IN_OUT 20 IO 25 MHz reference clock input/output (configurable)

RXD3 21 O MII mode: receive data output, bit 3 of RXD[3:0] nibble

CONFIG1 21 I pin strapping configuration input 1

RXD2 22 O MII mode: receive data output, bit 2 of RXD[3:0] nibble

CONFIG0 22 I pin strapping configuration input 0

RXD1 23 O MII mode: receive data output, bit 1 of RXD[3:0] nibble

RMII mode: receive data output, bit 1 of RXD[1:0] nibble

PHYAD2 23 I pin strapping configuration input for bit 2 of the PHY address used for the SMI

address/Cipher scrambler

RXD0 24 O MII mode: receive data output, bit 0 of RXD[3:0] nibble

RMII mode: receive data output, bit 0 of RXD[1:0] nibble

PHYAD1 24 I pin strapping configuration input for bit 1 of the PHY address used for the SMI

address/Cipher scrambler

O MII mode: external 25 MHz receive clock outputRXC 25

I MII reverse mode: 25 MHz receive clock input

I RMII mode: interface reference clock input (50 MHz external oscillator)REF_CLK 25

O RMII mode: interface reference clock output (25 MHz crystal at PHY or 25 MHz clock

at input of pin CLK_IN_OUT)

GND

[4]

26 G ground reference

DD(IO)

[3]

27 P 3.3 V I/O supply voltage

O MII mode: 25 MHz transmit clock outputTXC 28

I MII reverse mode: external 25 MHz transmit clock input

TXEN 29 I MII/RMII mode: transmit enable input (active-HIGH; weak pull-down)

TXD3 30 I MII mode: transmit data input, bit 3 of TXD[3:0] nibble (weak pull-down)

Table 2. Pin description...continued

Product data sheet Rev. 1 — 1 March 2021

5 / 58

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