################################################################################
# Vivado (TM) v2020.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA实现emmc读写代码
共1070个文件
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用7k325tfpga挂在江波龙的emmc进行写入递增数,在读取时芯片响应时间较长,导致写缓存溢出,需要更改。
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FPGA实现emmc读写代码 (1070个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 28KB
elaborate.bat 1KB
simulate.bat 1KB
compile.bat 846B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
EMMC_TOP.bin 4.14MB
EMMC_TOP.bin 3.93MB
EMMC_TOP.bin 3.73MB
EMMC_TOP.bin 3.73MB
EMMC_TOP.bin 3.41MB
EMMC_TOP.bit 4.14MB
EMMC_TOP.bit 3.98MB
EMMC_TOP.bit 3.93MB
EMMC_TOP.bit 3.92MB
EMMC_TOP.bit 3.73MB
EMMC_TOP.bit 3.73MB
EMMC_TOP.bit 3.41MB
xsim_1.c 24KB
xsim.dbg 167KB
EMMC_TOP_routed.dcp 12.9MB
EMMC_TOP_placed.dcp 10.6MB
EMMC_TOP_physopt.dcp 10.55MB
EMMC_TOP_opt.dcp 8.09MB
ila_512b.dcp 1.55MB
ila_512b.dcp 1.55MB
ila_512b.dcp 1.55MB
ila_256b.dcp 1.01MB
ila_256b.dcp 1.01MB
ila_256b.dcp 1.01MB
dbg_hub.dcp 419KB
dbg_hub.dcp 409KB
dbg_hub.dcp 400KB
dbg_hub.dcp 391KB
dbg_hub.dcp 380KB
dbg_hub.dcp 364KB
EMMC_TOP.dcp 228KB
vio_0.dcp 114KB
vio_0.dcp 114KB
vio_0.dcp 114KB
vio_0.dcp 113KB
sram_8192x16b.dcp 60KB
sram_8192x16b.dcp 60KB
sram_8192x16b.dcp 60KB
sram_4096x16b.dcp 42KB
sram_4096x16b.dcp 42KB
sram_4096x16b.dcp 42KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 11KB
compile.do 888B
compile.do 864B
compile.do 832B
compile.do 832B
compile.do 832B
compile.do 822B
compile.do 798B
compile.do 798B
compile.do 772B
compile.do 772B
compile.do 760B
compile.do 760B
compile.do 755B
compile.do 748B
compile.do 748B
compile.do 746B
compile.do 746B
compile.do 731B
compile.do 716B
compile.do 716B
compile.do 706B
compile.do 706B
compile.do 699B
compile.do 689B
simulate.do 334B
simulate.do 334B
simulate.do 333B
simulate.do 333B
simulate.do 333B
simulate.do 333B
simulate.do 304B
simulate.do 302B
simulate.do 302B
simulate.do 299B
simulate.do 299B
simulate.do 296B
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