<html>
<head>
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</script><title>Design Rule Verification Report</title>
</head>
<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD19\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2023/3/28</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">21:17:55</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:00</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\Administrator\Desktop\ST7789\PCB2.PcbDoc" class="file"><acronym title="C:\Users\Administrator\Desktop\ST7789\PCB2.PcbDoc">C:\Users\Administrator\Desktop\ST7789\PCB2.PcbDoc</acronym></a></td>
</tr>
</table>
</td>
<td class="column2">
<table class="DRC_summary_header">
<tr>
<td class="DRC_summary_header_col1">Warnings:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
</table>
</td>
</table><a name="IDEAJNWH4TLVD0J5WYAPK22REZUERT33UQ5SUWS5M5V0P34FOFG5JI"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br><table>
<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDXXDAC5DPBWNZ02C1Z14SP12XNLSZUOEKN3OORHWLM4SDJEOYPPJ">Clearance Constraint (Gap=0.054mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDTPLJ1ATIE2ZYCYUCYMDFGEJQGLWUQAPIV5AWIGJZLCIMXPCKLT0G">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAU1VBEVH0OBMI2VA3XC0XPJIMKJPP4FQ4HEOV3BRDAE0FY3KMGFB">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID4AVQMF1VB1GPBQIB1LNNZLQAIOZ0K123YYLMU3OCTNBJJCJYJLJI">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDFSRDHH3Z3LIQDQONGIHSZAYXTHE4GZJ3QLL1EFFQDIIOXRTQEZQG">Width Constraint (Min=0.254mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDIDTWP4NJPKU5MDB3VKEPLKFX4FT41215S0O1EYCA1BQGMRLKFDQM">Power Plane Connect Rule(Relief Connect )(Expansion=0.50
AD19_SCHLib_PcbLib-设计规则模板（20230328）.rar （98个子文件） 
AD19_SCHLib_PcbLib-设计规则模板（20230328） 
GB420.PcbLib 792KB WYJ110.PcbLib 1.22MB GB4201.PcbLib 756KB STM32F103C8T6.SCHLIB 37KB __Previews ST7789.SchDocPreview 26KB ST7789.SchDoc 45KB History 
PCB2.~(55).PcbDoc.Zip 907KB ST7789.~(6).SchDoc.Zip 6KB ST7789.~(2).PrjPcb.Zip 5KB PCB2.~(30).PcbDoc.Zip 890KB PCB2.~(7).PcbDoc.Zip 757KB PCB2.~(39).PcbDoc.Zip 890KB ST7789.~(8).SchDoc.Zip 6KB PCB2.~(33).PcbDoc.Zip 890KB PCB2.~(36).PcbDoc.Zip 890KB PCB2.~(53).PcbDoc.Zip 891KB PCB2.~(13).PcbDoc.Zip 757KB PCB2.~(56).PcbDoc.Zip 908KB ST7789.~(4).SchDoc.Zip 5KB ST7789.~(3).SchDoc.Zip 5KB PCB2.~(44).PcbDoc.Zip 890KB PCB2.~(15).PcbDoc.Zip 757KB PCB2.~(25).PcbDoc.Zip 758KB PCB2.~(46).PcbDoc.Zip 889KB 2P4M.~(4).SCHLIB.Zip 8KB ST7789.~(9).SchDoc.Zip 7KB PCB2.~(54).PcbDoc.Zip 891KB PCB2.~(14).PcbDoc.Zip 757KB PCB2.~(27).PcbDoc.Zip 758KB PCB2.~(43).PcbDoc.Zip 890KB ST7789.~(7).SchDoc.Zip 6KB PCB2.~(45).PcbDoc.Zip 889KB WYJ110.~(1).PcbLib.Zip 1.04MB PCB2.~(3).PcbDoc.Zip 24KB ST7789.~(13).SchDoc.Zip 7KB ST7789.~(5).SchDoc.Zip 6KB PCB2.~(31).PcbDoc.Zip 890KB ST7789.~(14).SchDoc.Zip 7KB PCB2.~(12).PcbDoc.Zip 757KB PCB2.~(22).PcbDoc.Zip 757KB PCB2.~(38).PcbDoc.Zip 890KB ST7789.~(10).SchDoc.Zip 7KB PCB2.~(26).PcbDoc.Zip 758KB PCB2.~(47).PcbDoc.Zip 895KB PCB2.~(5).PcbDoc.Zip 654KB PCB2.~(51).PcbDoc.Zip 892KB PCB2.~(28).PcbDoc.Zip 890KB PCB2.~(50).PcbDoc.Zip 892KB PCB2.~(57).PcbDoc.Zip 908KB 2P4M.~(3).SCHLIB.Zip 8KB PCB2.~(48).PcbDoc.Zip 898KB PCB2.~(19).PcbDoc.Zip 757KB PCB2.~(52).PcbDoc.Zip 892KB PCB2.~(37).PcbDoc.Zip 890KB PCB2.~(9).PcbDoc.Zip 757KB PCB2.~(16).PcbDoc.Zip 757KB PCB2.~(20).PcbDoc.Zip 757KB PCB2.~(10).PcbDoc.Zip 757KB 2P4M.~(1).SCHLIB.Zip 7KB PCB2.~(32).PcbDoc.Zip 890KB PCB2.~(1).PcbDoc.Zip 24KB WYJ110.~(2).PcbLib.Zip 1.04MB PCB2.~(42).PcbDoc.Zip 891KB PCB2.~(2).PcbDoc.Zip 24KB PCB2.~(4).PcbDoc.Zip 654KB PCB2.~(17).PcbDoc.Zip 757KB PCB2.~(6).PcbDoc.Zip 654KB PCB2.~(23).PcbDoc.Zip 757KB PCB2.~(34).PcbDoc.Zip 890KB 2P4M.~(2).SCHLIB.Zip 8KB PCB2.~(21).PcbDoc.Zip 757KB PCB2.~(49).PcbDoc.Zip 892KB PCB2.~(11).PcbDoc.Zip 757KB PCB2.~(41).PcbDoc.Zip 892KB PCB2.~(40).PcbDoc.Zip 890KB PCB2.~(58).PcbDoc.Zip 908KB ST7789.~(2).SchDoc.Zip 3KB PCB2.~(8).PcbDoc.Zip 757KB PCB2.~(24).PcbDoc.Zip 757KB ST7789.~(11).SchDoc.Zip 7KB ST7789.~(1).PrjPcb.Zip 4KB ST7789.~(12).SchDoc.Zip 7KB PCB2.~(29).PcbDoc.Zip 890KB PCB2.~(18).PcbDoc.Zip 757KB ST7789.~(1).SchDoc.Zip 1KB PCB2.~(35).PcbDoc.Zip 890KB Project Logs for ST7789 PCB2 PCB ECO 2023-3-27 23-21-22.LOG 929B ST7789 SCH ECO 2023-3-27 22-31-25.LOG 399B PCB2 PCB ECO 2023-3-27 22-44-00.LOG 4KB ST7789.PrjPcb 41KB GB4202.PcbLib 689KB ST7789.PrjPcbStructure 48B PCB2.PcbDoc 1.13MB Project Outputs for ST7789 Design Rule Check - PCB2.drc 1KB
Design Rule Check - PCB2.html 10KB 2P4M.SCHLIB 54KB STM32F103C8T6核心板.PcbLib 75KB GB4203.PcbLib 0B资源评论
