【免费】安森美PYTHON1300/500/300CMOS图像传感器datasheet资源-CSDN文库

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April, 2018 − Rev. 5

1 Publication Order Number:

NOIP1SN1300A/D

NOIP1SN1300A

PYTHON 1.3/0.5/0.3 MegaPixels

Global Shutter CMOS

Image Sensors

FEATURES

• Size Options:

♦ PYTHON 300: 640 x 480 Active Pixels, 1/4” Optical Format

♦ PYTHON 500: 800 x 600 Active Pixels, 1/3.6” Optical Format

♦ PYTHON 1300: 1280 x 1024 Active Pixels, 1/2” Optical Format

• Data Output Options:

♦ P1−SN/SE/FN: 4 LVDS Data Channels

♦ P2−SN/SE: 10 bit Parallel

♦ P3−SN/SE/FN: 2 LVDS Data Channels

• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with In-pixel CDS

• Monochrome (SN), Color (SE) and NIR (FN)

• Zero Row Overhead Time (ZROT) Mode Enabling Higher Frame

Rate

• Frame Rate at Full Resolution, 4 LVDS Data Channels

(P1−SN/SE/FN only)

♦ 210/165 frames per second @ SXGA (ZROT/NROT)

♦ 545/385 frames per second @ SVGA (ZROT/NROT)

♦ 815/545 frames per second @ VGA (ZROT/NROT)

• Frames Rate at Full Resolution (CMOS)

♦ 50/43 Frames per Second @ SXGA (ZROT/NROT)

• On−chip 10−bit Analog−to−Digital Converter (ADC)

• Four/Two/One LVDS High Speed Serial Outputs or

Parallel CMOS Output

• Random Programmable Region of Interest (ROI)

Readout

• Serial Peripheral Interface (SPI)

• Automatic Exposure Control (AEC)

• Phase Locked Loop (PLL)

• High Dynamic Range (HDR) Modes Possible

• Dual Power Supply (3.3 V and 1.8 V)

• −40°C to +85°C Operational Temperature Range

• 48−pin LCC

• Power Dissipation:

♦ 620 mW (P1, 4 LVDS, ZROT)

♦ 420 mW (P1, P3, 2 LVDS, NROT)

♦ 270 mW (P1, P3, 1 LVDS, NROT)

♦ 420 mW (P2, ZROT)

• These Devices are Pb−Free and are RoHS Compliant

APPLICATIONS

• Machine Vision

• Motion Monitoring

• Security

• Barcode Scanning (2D)

DESCRIPTION

The PYTHON 300, PYTHON 500, and PYTHON 1300

image sensors utilize high sensitivity 4.8 mm x 4.8 mm pixels

that support low noise “pipelined” and “triggered” global

shutter readout modes. The sensors support correlated

double sampling (CDS) readout, reducing noise and

increasing dynamic range.

The image sensors have on−chip programmable gain

amplifiers and 10−bit A/D converters. The integration time

and gain parameters can be reconfigured without any visible

image artifact. Optionally the on−chip automatic exposure

control loop (AEC) controls these parameters dynamically.

The image’s black level is either calibrated automatically or

can be adjusted by adding a user programmable offset.

A high level of programmability using a four wire serial

peripheral interface enables the user to read out specific

regions of interest. Up to eight regions can be programmed,

achieving even higher frame rates.

The image data interface of the P1−SN/SE/FN devices

consists of four LVDS lanes, enabling frame rates up to 210

frames per second in Zero ROT mode for the

PYTHON 1300. Each channel runs at 720 Mbps. A separate

synchronization channel containing payload information is

provided to facilitate the image reconstruction at the

receiving end. The P2−SN/SE devices provide a parallel

CMOS output interface at reduced frame rate. The

P3−SN/SE/FN devices are the same as the P1−SN/SE/FN

but with only two of the four LVDS data channels enabled,

facilitating frame rates of 90 frames per second in Normal

ROT for the PYTHON 1300.

www.onsemi.com

Figure 1. PYTHON 1300

NOIP1SN1300A

www.onsemi.com

The devices are provided in a 48−pin LCC package and are available in monochrome, Bayer color, and extended

near−infrared (NIR) configurations.

ORDERING INFORMATION

Part Number Description Package

PYTHON 1300

NOIP1SN1300A−QDI

1.3 Megapixel, Monochrome, LVDS Output

48−pin LCC

NOIP1SE1300A−QDI 1.3 Megapixel, Bayer Color, LVDS Output

NOIP1FN1300A−QDI 1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output

NOIP2SN1300A−QDI 1.3 Megapixel, Monochrome, CMOS (parallel) Output

NOIP2SE1300A−QDI 1.3 Megapixel, Bayer Color, CMOS (parallel) Output

NOIP1SN1300A−QTI 1.3 Megapixel, Monochrome, LVDS Output, Protective Foil

NOIP1SE1300A−QTI 1.3 Megapixel, Bayer Color, LVDS Output, Protective Foil

NOIP1FN1300A−QTI 1.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

NOIP3SN1300A−QDI 1.3 Megapixel, 2 LVDS Outputs, Monochrome

NOIP3FN1300A−QDI 1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome

NOIP3SE1300A−QDI 1.3 Megapixel, 2 LVDS Outputs, Color

NOIP3SN1300A−QTI 1.3 Megapixel, 2 LVDS Outputs, Monochrome, Protective Foil

NOIP3FN1300A−QTI 1.3 Megapixel, 2 LVDS Outputs, NIR enhanced Monochrome, Protective Foil

NOIP3SE1300A−QTI 1.3 Megapixel, 2 LVDS Outputs, Color, Protective Foil

PYTHON 500

NOIP1SN0500A−QDI

0.5 Megapixel, Monochrome, LVDS Output

48−pin LCC

NOIP1SE0500A−QDI 0.5 Megapixel, Bayer Color, LVDS Output

NOIP1FN0500A−QDI 0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output

NOIP1SN0500A−QTI 0.5 Megapixel, Monochrome, LVDS Output, Protective Foil

NOIP1SE0500A−QTI 0.5 Megapixel, Bayer Color, LVDS Output, Protective Foil

NOIP1FN0500A−QTI 0.5 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

PYTHON 300

NOIP1SN0300A−QDI

0.3 Megapixel, Monochrome, LVDS Output

48−pin LCC

NOIP1SE0300A−QDI 0.3 Megapixel, Bayer Color, LVDS Output

NOIP1FN0300A−QDI 0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output

NOIP1SN0300A−QTI 0.3 Megapixel, Monochrome, LVDS Output, Protective Foil

NOIP1SE0300A−QTI 0.3 Megapixel, Bayer Color, LVDS Output, Protective Foil

NOIP1FN0300A−QTI 0.3 Megapixel, Monochrome with enhanced NIR, LVDS Output, Protective Foil

The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 4 LVDS interface; the P2−SN/SE

base part references the mono and color versions of the CMOS interface; the P3−SN/SE/FN base part references the mono,

color and NIR enhanced version of the 2 LVDS interface. More details on the part number coding can be found at

http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF

Production Package Mark

Line 1: NOIPyxxRRRRA where y is either “1” for 4 LVDS Outputs, “2” for CMOS Parallel Output, “3” for 2 LVDS Outputs,

where xx denotes mono micro lens (SN) or color micro lens (SE) or NIR micro lens (FN)

RRRR is the resolution (1300), (0500) or (0300)

Line 2: −QDI (without protective foil), −QTI (with protective foil)

Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code

NOIP1SN1300A

www.onsemi.com

SPECIFICATIONS

Key Specifications

Table 1. GENERAL SPECIFICATIONS

Parameter Specification

Pixel type In−pixel CDS. Global shutter pixel

architecture

Shutter type Pipelined and triggered global shutter

Frame rate

Zero ROT/

Normal ROT

mode

P1−SN/SE/FN:

PYTHON 300: 815/545 fps

PYTHON 500: 545/385 fps

PYTHON 1300: 210/165 fps

P2−SN/SE: 50/43 fps

P3−SN/SE/FN: NA/90 fps

Master clock P1, P3−SN/SE/FN:

72 MHz when PLL is used,

360 MHz (10−bit) / 288 MHz (8−bit)

when PLL is not used

P2−SN/SE: 72 MHz

Windowing 8 Randomly programmable windows. Nor-

mal, sub−sampled and binned readout

modes

ADC resolution 10−bit, 8−bit (Note 1)

LVDS outputs P1−SN/SE/FN: 4/2/1 data + sync + clock

P3−SN/SE/FN: 2/1 data + sync + clock

CMOS outputs P2−SN/SE: 10−bit parallel output,

frame_valid, line_valid, clock

Data rate P1−SN/SE/FN:

4 x 720 Mbps (10−bit) /

4 x 576 Mbps (8−bit)

P2−SN/SE: 72 Mhz

P3−SN/SE/FN: 2 x 720 Mbps (10−bit)

Power

dissipation

(10−bit mode)

P1−SN/SE/FN: 620 mW (4 data channels)

P1, P3−SN/SE/FN: 420 mW (2 data ch.)

P1, P3−SN/SE/FN: 270 mW (1 data ch.)

P2−SN/SE: 420 mW

Package type 48−pin LCC

Table 2. ELECTRO−OPTICAL SPECIFICATIONS

Parameter Specification

Active pixels PYTHON 300: 640 (H) x 480 (V)

PYTHON 500: 800 (H) x 600 (V)

PYTHON 1300: 1280 (H) x 1024 (V)

Pixel size

4.8 mm x 4.8 mm

Conversion gain 0.096 LSB10/e

−

140 mV/e

−

Dark temporal noise < 9 e

−

(Normal ROT, 1x gain)

< 7 e

−

(Normal ROT, 2x gain)

Responsivity

at 550 nm

7.7 V/lux.s

Parasitic Light

Sensitivity (PLS)

<1/8000

Full Well Charge 10000 e

−

Quantum Efficiency

at 550 nm

56%

Pixel FPN < 1.0 LSB10

PRNU < 2% or 10 LSB10 on half scale

response of 525LSB10

MTF 68% @ 535 nm − X−dir & Y−dir

PSNL at 20°C 120 LSB10/s, 1200 e

−

Dark signal at 20°C 5 e

−

/s, 0.5 LSB10/s

Dynamic Range > 60 dB in global shutter mode

Signal to Noise Ratio

(SNR max)

40 dB

Table 3. RECOMMENDED OPERATING RATINGS (Note 2)

Symbol

Description Min Max Unit

Operating temperature range −40 85 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)

Symbol

Parameter Min Max Unit

ABS (1.8 V supply group) ABS rating for 1.8 V supply group –0.5 2.2 V

ABS (3.3 V supply group) ABS rating for 3.3 V supply group –0.5 4.3 V

ABS storage temperature range −40 +150 °C

ABS storage humidity range at 85°C 85 %RH

Electrostatic discharge (ESD)

Human Body Model (HBM): JS−001−2010 2000

Charged Device Model (CDM): JESD22−C101 500

LU Latch−up: JESD−78 100 mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.

2. Operating ratings are conditions in which operation of the device is intended to be functional.

3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer

to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.

4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can

absorb moisture if the sensor is placed in a high % RH environment.

NOIP1SN1300A

www.onsemi.com

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for T

= T

MIN

to T

MAX

, all other limits T

= +30°C. (Notes 5, 6, 7, 8 and 9)

Parameter

Description Min Typ Max Unit

Power Supply Parameters − P1 − SN/SE/FN LVDS (ZROT)

(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)

vdd_33

Supply voltage, 3.3 V 3.2 3.3 3.4 V

Idd_33 Current consumption 3.3 V supply 140 mA

vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V

Idd_18 Current consumption 1.8 V supply 80 mA

vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V

Idd_pix Current consumption pixel supply 5 mA

Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

P1−SN/SE/FN, 4 LVDS, ZROT

620 mW

Pstby_lp Power consumption in low power standby mode 50 mW

Popt Power consumption at lower pixel rates Configurable

Power Supply Parameters − P3 − SN/SE/FN LVDS (NROT)

(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)

vdd_33

Supply voltage, 3.3 V 3.2 3.3 3.4 V

Idd_33 Current consumption 3.3 V supply (2 / 1 LVDS) 95 / 55 mA

vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V

Idd_18 Current consumption 1.8 V supply (2 / 1 LVDS) 55 / 45 mA

vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V

Idd_pix Current consumption pixel supply (2 / 1 LVDS) 2 / 1 mA

Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

P3−SN/SE/FN, 2 LVDS, NROT

P3−SN/SE/FN, 1 LVDS, NROT

420

270

Pstby_lp Power consumption in low power standby mode 50 mW

Popt Power consumption at lower pixel rates Configurable

Power Supply Parameters − P2−SN/SE CMOS

vdd_33

Supply voltage, 3.3 V 3.2 3.3 3.4 V

Idd_33 Current consumption 3.3 V supply 120 mA

vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V

Idd_18 Current consumption 1.8 V supply 10 mA

vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V

Idd_pix Current consumption pixel supply 1 mA

Ptot Total power consumption 420 mW

Pstby_lp Power consumption in low power standby mode 50 mW

Popt Power consumption at lower pixel rates Configurable

I/O − P1−SN/SE/FN, P3−SN/SE/FN LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed

fserdata

Data rate on data channels

DDR signaling − 4 data channels, 1 synchronization channel

720 Mbps

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. All parameters are characterized for DC conditions after thermal equilibrium is established.

6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is

recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high

impedance circuit.

7. Minimum and maximum limits are guaranteed through test and design.

8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.

9. For power supply management recommendations, please refer to Application Note AND9158.

NOIP1SN1300A

www.onsemi.com

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for T

= T

MIN

to T

MAX

, all other limits T

= +30°C. (Notes 5, 6, 7, 8 and 9)

Parameter UnitMaxTypMinDescription

fserclock Clock rate of output clock

Clock output for mesochronous signaling

360 MHz

Vicm LVDS input common mode level 0.3 1.25 1.8 V

Tccsk Channel to channel skew (Training pattern allows per channel

skew correction)

50 ps

I/O − P2−SN/SE CMOS (JEDEC− JESD8C−01): Conforming to standard/additional specifications and deviations listed

fpardata

Data rate on parallel channels (10−bit) 72 Mbps

Cout Output load (only capacitive load) 10 pF

tr Rise time (10% to 90% of input signal) 2.5 4.5 6.5 ns

tf Fall time (10% to 90% of input signal) 2 3.5 5 ns

Electrical Interface − P1 − SN/SE/FN LVDS

fin

Input clock rate when PLL used 72 MHz

fin Input clock when LVDS input used 360 MHz

tidc Input clock duty cycle when PLL used 45 50 55 %

tj Input clock jitter 20 ps

ratspi

(= fin/fspi)

10−bit (4 LVDS channels), PLL used 6

10−bit (2 LVDS channels), PLL used 12

10−bit (1 LVDS channel), PLL used 24

10−bit (4 LVDS channels), LVDS input used 30

10−bit (2 LVDS channels), LVDS input used 60

10−bit (1 LVDS channel), LVDS input used 120

8−bit (4 LVDS channels), PLL used 6

8−bit (2 LVDS channels), PLL used 12

8−bit (1 LVDS channel), PLL used 24

8−bit (4 LVDS channels), LVDS input used 24

8−bit (2 LVDS channels), LVDS input used 48

8−bit (1 LVDS channel), LVDS input used 96

Electrical Interface − P2−SN/SE CMOS

fin

Input clock rate 72 MHz

tidc Input clock duty cycle 45 50 55 %

tj Input clock jitter 20 ps

ratspi

(= fin/fspi)

10−bit, PLL bypassed 24

Electrical Interface − P3 − SN/SE/FN LVDS

fin

Input clock rate when PLL used 72 MHz

fin Input clock when LVDS input used 360 MHz

tidc Input clock duty cycle when PLL used 45 50 55 %

tj Input clock jitter 20 ps

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. All parameters are characterized for DC conditions after thermal equilibrium is established.

6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is

recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high

impedance circuit.

7. Minimum and maximum limits are guaranteed through test and design.

8. Refer to ACSPYTHON1300 available at the Image Sensor Portal for detailed acceptance criteria specifications.

9. For power supply management recommendations, please refer to Application Note AND9158.

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