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<title>Sample Waveforms for lpm_ram_dq0.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file lpm_ram_dq0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design lpm_ram_dq0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design lpm_ram_dq0.vhd has one read/write port. The read/write port has 256 words of 16 bits each. The core uses a different clock enable than the input registers. The output of the read/write port is unregistered. </P>
<CENTER><img src=lpm_ram_dq0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. </P>
<CENTER><img src=lpm_ram_dq0_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. Actual write into the RAM happens at the rising edge or falling edge of the write clock, depending on whether the RAM blocks are assigned to M-RAM or not. In the sample waveforms, they are shown to be on the falling edge of the write clock. The clock enable on the write side input registers are disabled. During a write cycle, the new data flows through to the output. </P>
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Quartus2 cpu
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2010-05-24
17:03:37
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Quartus2 cpu （209个子文件） 
SL.vhd.bak 3KB ALU.vhd.bak 2KB MAR.vhd.bak 813B MBR.vhd.bak 806B BR.vhd.bak 678B PC.vhd.bak 664B ACC.vhd.bak 658B IR.vhd.bak 575B CAR.vhd.bak 491B CBR.vhd.bak 491B CPU.bdf 36KB CPU_ALL.bdf 26KB CU.bdf 19KB CU_ALL.bdf 19KB CPU.cmp.bpm 924B CPU.map.bpm 883B CU_ALL.bsf 5KB CBR.bsf 4KB ALU.bsf 3KB SL.bsf 3KB MBR.bsf 3KB lpm_ram_dq0.bsf 2KB MAR.bsf 2KB lpm_rom1.bsf 2KB PC.bsf 2KB lpm_rom0.bsf 2KB BR.bsf 2KB IR.bsf 2KB ACC.bsf 2KB CAR.bsf 2KB CPU.cmp.cdb 122KB CPU.fnsim.cdb 89KB CPU.cmp_bb.cdb 39KB CPU.rtlv_sg.cdb 30KB CPU.sgdiff.cdb 27KB CPU.map.cdb 26KB CPU.map_bb.cdb 26KB CPU.pre_map.cdb 24KB CPU.(12).cnf.cdb 13KB CPU.rtlv_sg_swap.cdb 5KB CPU.(5).cnf.cdb 4KB CPU.(0).cnf.cdb 4KB CPU.(15).cnf.cdb 2KB CPU.(18).cnf.cdb 2KB CPU.(17).cnf.cdb 2KB CPU.(10).cnf.cdb 2KB CPU.(4).cnf.cdb 2KB CPU.(2).cnf.cdb 2KB CPU.(27).cnf.cdb 2KB CPU.(26).cnf.cdb 1KB CPU.(11).cnf.cdb 1KB CPU.(14).cnf.cdb 1KB CPU.(24).cnf.cdb 1KB CPU.(25).cnf.cdb 1KB CPU.(9).cnf.cdb 1KB CPU.(28).cnf.cdb 1KB CPU.(7).cnf.cdb 1KB CPU.(8).cnf.cdb 1KB CPU.(3).cnf.cdb 1KB CPU.(20).cnf.cdb 1KB CPU.(30).cnf.cdb 1KB CPU.(23).cnf.cdb 1KB CPU.(16).cnf.cdb 1KB CPU.(29).cnf.cdb 1KB CPU.(19).cnf.cdb 1KB CPU.signalprobe.cdb 1KB CPU.(13).cnf.cdb 847B CPU.(1).cnf.cdb 723B CPU.(6).cnf.cdb 600B CPU.eco.cdb 161B lpm_ram_dq0.cmp 1KB lpm_rom1.cmp 1000B lpm_rom0.cmp 967B CPU.sim.cvwf 6KB CPU.db_info 137B CPU.dbp 0B CPU.asm_labs.ddb 794KB CPU.cmp0.ddb 369KB CPU.cmp2.ddb 92KB CPU.tis_db_list.ddb 174B CPU.done 26B CPU.cmp.ecobp 28B CPU.map.ecobp 28B CPU.eds_overflow 5B CPU.fnsim.hdb 95KB CPU.sgdiff.hdb 24KB CPU.map.hdb 24KB CPU.map_bb.hdb 24KB CPU.pre_map.hdb 24KB CPU.rtlv.hdb 24KB CPU.cmp.hdb 23KB CPU.cmp_bb.hdb 23KB CPU.sim.hdb 3KB CPU.(12).cnf.hdb 1KB CPU.(0).cnf.hdb 1KB CPU.(5).cnf.hdb 916B CPU.(24).cnf.hdb 886B CPU.(19).cnf.hdb 861B CPU.(29).cnf.hdb 856B CPU.(15).cnf.hdb 837B共 209 条
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资源评论
zuimengqianlin2012-06-28只有组件，最主要的控制器之类没有
superallen0012013-12-16我也是想看控制器，可惜没有
