################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA FFT(IFFT)算法 (379个子文件)
__synthesis_is_complete__ 0B
_info 14KB
_info 3KB
_info 122B
_info 122B
_vmake 29B
_vmake 29B
xsim.ini.bak 23KB
elaborate.bat 946B
compile.bat 840B
simulate.bat 807B
simulate.bat 806B
compile.bat 800B
runme.bat 229B
xsim_1.c 11KB
data.coe 96B
data.coe 96B
data.coe 96B
data.coe 96B
xsim.dbg 79KB
fifo_generator_0.dcp 83KB
fifo_generator_0.dcp 71KB
rom_ifft.dcp 61KB
fifo_generator_0.dcp 60KB
fifo_generator_0.dcp 60KB
fifo_generator_0.dcp 60KB
fifo_generator_0.dcp 59KB
rom_ip.dcp 23KB
rom_ip.dcp 23KB
rom_ip.dcp 23KB
rom_ip.dcp 23KB
rom_ifft_sim_compile.do 1KB
rom_fft_sim_compile.do 1KB
compile.do 640B
rom_ifft_sim_simulate.do 636B
rom_fft_sim_simulate.do 632B
compile.do 616B
compile.do 575B
compile.do 565B
rom_ifft_sim_wave.do 345B
rom_fft_sim_wave.do 344B
simulate.do 327B
simulate.do 327B
simulate.do 325B
simulate.do 209B
elaborate.do 197B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
基于FPGA的FFT及IFFT的实现.docx 105KB
xsimk.exe 150KB
run.f 483B
run.f 467B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
modelsim.ini 32KB
xsim.ini 23KB
xsim.ini 22KB
xsimSettings.ini 1KB
webtalk.jou 792B
webtalk_15712.backup.jou 792B
vivado.jou 654B
vivado.jou 640B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 22KB
compile.log 4KB
elaborate.log 2KB
simulate.log 2KB
vivado.log 1KB
summary.log 897B
summary.log 897B
webtalk.log 861B
webtalk_15712.backup.log 861B
compile.log 696B
xvlog.log 696B
simulate.log 367B
xsimkernel.log 331B
xsimcrash.log 0B
fft.lpr 290B
xsim.mem 16KB
rom_ip.mif 36B
rom_ip.mif 36B
rom_ip.mif 36B
rom_ip.mif 36B
xsim_0.win64.obj 97KB
xsim_1.win64.obj 8KB
elab.opt 202B
vivado.pb 38KB
xelab.pb 4KB
xvlog.pb 1KB
rom_ifft_utilization_synth.pb 224B
rom_fft_sim_vlog.prj 337B
vlog.prj 161B
_lib.qdb 64KB
_lib.qdb 48KB
_lib.qdb 48KB
_lib.qdb 48KB
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