PLL 锁相环芯片HMC833 HMC830芯片FPGA控制VERILOG驱动程序源码
module HMC833(
clk,rst,din_N,din_F,din_Rdiv,trig_in, //trig_in posedge pulse valid
SEN,SDI,SCK,
park_cs,
vco_r2,
vco_r3
`ifdef Simulation
,cstate,TimeCnt,IdleCnt,init,regcnt
`endif
);
input clk,rst,din_N,din_F,din_Rdiv,trig_in;
input wire [15:0] vco_r2;
input wire [15:0] vco_r3;
output SEN,SDI,SCK;
output reg park_cs;
`ifdef Simulation
output cstate,TimeCnt,IdleCnt,init,regcnt;
`endif
wire