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PRELIMINARY: ATHEROS CONFIDENTIAL • 1

Data Sheet

, Atheros Driven

, Atheros XR

, Driving the Wireless Future

, ROCm

, Super A/G

Super G

, Total 802.11

, and Wake on Wireless

are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air is

Cleaner at 5-GHz™, XSPAN

, Wireless Future. Unleashed Now.

, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a

registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.

s C

ntia

November 2012

AR6103 ROCm

Integrated 802.11n

General Description

The AR6103 is a complete, small form factor

802.11 b/g/n Wi-Fi solution optimized for low-

power, low-cost, and highly integrated mobile

and portable consumer electronic devices. The

device integrates all Wi-Fi functionality in a

package friendly to low-cost PCB design,

requiring only a few external bypass capacitors

and connection to an antenna.

The AR6103 is part of the 3rd generation

ROCm™ family

of mobile 11n devices,

employing the world's lowest power

consumption embedded architecture.

The AR6103 can support numerous external

uetooth devices, and includes advanced PTA

coexistence support. A flexible architecture

enables optional customization to meet

customer specific profiles and use cases.

On-chip high-efficiency high-output EPA™

pow

er amplifier with zero calibration,

integrated LNAs, integrated receive and

transmit RF matching circuits, integrated

reference crystal, and integrated T/R switch

eliminate the need for external RF components

and enable direct antenna connection.

Ultra low power consumption radio

chitecture and proprietary power save

technologies extend battery life. On-chip high-

efficiency PMU (power management unit)

enables direct-connect to battery, eliminating

the need for external regulators. An on-chip

embedded CPU handles complete 11n

processing to minimize host processor loading.

AR6103 Block Diagram

for waching

customer

Atheros Communications, Inc. AR6103 ROCm® Data Sheet • 3

PRELIMINARY: ATHEROS CONFIDENTIALNovember 2012 • 3

Table of Contents

1 Features Summary ......................... 5

1.1 Overview ............................................... 5

1.2 Radio Front End

................................... 5

1.3 Power Management

............................. 5

1.4 Manufacturing Calibration

................. 5

1.5 Internal One-Time Programmable

Memory 5

1.6 Reference Frequency

............................ 5

1.7 Internal Sleep Clock

............................. 5

1.8 Interfaces

................................................ 5

1.8.1 Standard Host Interface

............... 5

1.9 Mobile 802.11n

...................................... 6

1.10 Advanced Wi-Fi Features

.................... 7

1.10.1 AP Mode (Mobile Hot Spot) .... 8

1.10.2 DirectConnect™ (Peer-to-Peer)

.. 8

1.11 Host Offloading (Wi-Fi)

...................... 8

1.11.1 TCP Checksum .......................... 8

1.11.2 Security Negotiation

.................... 8

2 Wi-Fi Functional Description ..... 9

2.1 Overview ............................................... 9

2.2 XTENSA CPU

....................................... 9

2.3 Virtual Memory Controller (VMC)

.... 9

2.4 AHB and APB Blocks

........................... 9

2.5 GPIO

....................................................... 9

2.6 MBOX

................................................... 10

2.7 Debug UART

....................................... 10

2.8 Reset Control

....................................... 10

2.8.1 CPU Reset

................................. 10

2.9 Reset Sequence

.................................... 10

2.10 Power Management Unit

.................. 10

2.11 Power Transition Diagram

................ 11

2.11.1 Hardware Power States

.......... 11

2.11.2 Sleep State Management ............ 11

2.12 System Clocking (RTC Block)

........... 13

2.12.1 High Speed Clocking

.............. 13

2.12.2 Low-Speed Clocking .................. 13

2.12.3 Sleep Clock Option

..................... 14

2.12.4 Interface Clock ............................ 14

2.13 Front End Control

.............................. 14

2.14 MAC/BB/RF Block

........................... 14

2.15 Baseband Block

................................... 14

2.16 Design for Test

.................................... 14

3 Electrical Characteristics ............15

3.1 Absolute Maximum Ratings ............. 15

3.2 Recommended Operating

Conditions

........................................... 16

3.3 DC Electrical Characteristics

............ 17

3.4 Radio Receiver Characteristics

......... 20

3.5 Radio Transmitter Characteristics

... 21

3.6 AR6103 Synthesizer Characteristics 22

3.7 Typical Power Consumption

Performance

........................................ 23

3.7.1 Measurement Conditions

for Low Power States .............. 23

3.7.2 Measurement Conditions for

Continuous Receive [2.4 GHz

Operation] ................................... 24

3.7.3 Measurement Conditions for

Continuous Transmit [2.4 GHz

Operation] ................................... 24

4 Pin Assignments and Descriptions

5 Package Dimensions ...................33

6 Assembly Guidelines

..................35

6.1 Solder Material Information ............. 35

7 Design Guidelines .......................37

7.1 Application Schematic ....................... 37

7.2 Bluetooth Coexistence

....................... 38

7.3 Antenna Diversity Option

................ 38

7.4 Power Supply and the PMU

............. 38

7.4.1 On-chip PMU Configuration . 38

7.4.2 External Supply Configuration 40

7.4.3 Designing for External Supplies

with PMU Option

....................... 40

7.5 Power Supply Bypassing

.................. 40

7.6 Sleep Clock Option

............................ 41

7.7 Testability Recommendations

.......... 41

for waching

customer

Atheros Communications, Inc. AR6103 ROCm® Data Sheet • 5

PRELIMINARY: ATHEROS CONFIDENTIAL November 2012 • 5

: P

ract

ist

ics

ubje

t t

han

- At

s C

ial

1. Features Summary

1.1 Overview

The AR6103 is a single package combination

IEEE 802.11 (b, g, n) based on cutting edge

technology from the AR6003 ROCm™ family

of mobile 11n. The AR6103 contains 802.11

including full digital MAC and baseband

engines handling all 802.11b (CCK), 11g/n

(OFDM). An embedded low-power CPU cores

minimize host loading and maximize flexibility

to support customer specific profiles and use

cases.

The AR6103 is architected for ultra-low power

consumption,

with near zero power

consumption in idle and stand-by modes,

enabling users to leave Wi-Fi "always on".

A pin-compatible standalone 802.11n plus

advanced Bluetooth

device (AR6133) is also

available.

1.2 Radio Front End

The AR6103 features a high-power high-

efficiency on-chip power amplifier that

features the following:

■

Atheros proprietary EPA™ linearization

technology for Wi-Fi.

■

Highly integrated LNAs .

■

Integrated receive and transmit RF

matching and switching enable direct

antenna connection with high performance,

low power consumption, and near-zero

RBOM for lowest solution cost.

1.3 Power Management

The AR6103 features direct connection to

battery, eliminating the need for external

regulators and/or PMU. The AR6103

supports operating voltage from 4.2V down to

3.1V and is tolerant of momentary overvoltage

up to 5.5V. An on-chip switching regulator

supports PWM mode and burst mode to

optimize power efficiency under both peak

operation and low load conditions. An internal

PMU with separate analog and digital LDO

regulation provides superior noise isolation for

analog and digital supplies.

An optional PMU bypass mode, disables the

on-chi

p switching regulator to allow an

external 1.8V regulated supply to directly

power the device, if so desired.

The AR6103 power management engine

utilizes advanced

power save techniques such

as: gating clocks to idle or inactive blocks,

voltage scaling to specific blocks in certain

states, fast start and settling circuits to reduce

Tx and active duty cycles, CPU frequency

scaling, and other techniques to optimize

power consumption across all operation states.

1.4 Manufacturing Calibration

The AR6103 utilizes internal self-calibration

and BIST (built-in self test) circuits to maintain

optimal performance over temperature, time

and process variation. The AR6103 is delivered

fully tested and does not require any customer

manufacturing line calibration.

1.5 Internal One-Time Programmable

Memory

The AR6103 includes internal one-time

programmable memory which may be used to

store the device MAC address, eliminating the

need for external EEPROM.

1.6 Reference Frequency

The AR6103 incorporates an on-chip 26MHz

(20ppm) reference frequency source.

Internally, the system reference frequency is

sleep regulated and gated to enable the internal

crystal to be powered down when the device is

in sleep mode. Manufacturing calibration of

the crystal is not required, but is supported as

an option.

1.7 Internal Sleep Clock

The AR6103 incorporates integrated on-chip

low power sleep clocks to regulate internal

timing, eliminating the need for any external

32kHz real time clocks or crystal oscillators.

1.8 Interfaces

The AR6103 supports SDIO 1.x and the latest

2.0 standard.

1.8.1 Standard Host Interface

The AR6103 supports industry standard SDIO

2.0 (50MHz, 4-bit and 1-bit) and GSPI (Generic

SPI) for Wi-Fi.

for waching

customer

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