TMS320C674x DSP
CPU and Instruction Set
Reference Guide
Literature Number: SPRUFE8A
May 2010
2
SPRUFE8A–May 2010
Copyright © 2010, Texas Instruments Incorporated
Contents
Preface ...................................................................................................................................... 17
1 Introduction ...................................................................................................................... 19
1.1 Overview .................................................................................................................... 20
1.2 DSP Features and Options ............................................................................................... 20
1.3 DSP Architecture .......................................................................................................... 22
1.3.1 Central Processing Unit (CPU) ................................................................................. 23
1.3.2 Internal Memory .................................................................................................. 23
1.3.3 Memory and Peripheral Options ................................................................................ 23
2 CPU Data Paths and Control ............................................................................................... 25
2.1 Introduction ................................................................................................................. 26
2.2 General-Purpose Register Files ......................................................................................... 26
2.3 Functional Units ............................................................................................................ 29
2.4 Register File Cross Paths ................................................................................................ 30
2.5 Memory, Load, and Store Paths ......................................................................................... 31
2.6 Data Address Paths ....................................................................................................... 31
2.7 Galois Field ................................................................................................................. 31
2.7.1 Special Timing Considerations ................................................................................. 33
2.8 Control Register File ...................................................................................................... 34
2.8.1 Register Addresses for Accessing the Control Registers ................................................... 35
2.8.2 Pipeline/Timing of Control Register Accesses ................................................................ 35
2.8.3 Addressing Mode Register (AMR) ............................................................................. 36
2.8.4 Control Status Register (CSR) .................................................................................. 38
2.8.5 Galois Field Polynomial Generator Function Register (GFPGFR) ......................................... 40
2.8.6 Interrupt Clear Register (ICR) ................................................................................... 41
2.8.7 Interrupt Enable Register (IER) ................................................................................. 42
2.8.8 Interrupt Flag Register (IFR) .................................................................................... 43
2.8.9 Interrupt Return Pointer Register (IRP) ........................................................................ 43
2.8.10 Interrupt Set Register (ISR) .................................................................................... 44
2.8.11 Interrupt Service Table Pointer Register (ISTP) ............................................................. 45
2.8.12 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) ............................................. 45
2.8.13 E1 Phase Program Counter (PCE1) .......................................................................... 46
2.9 Control Register File Extensions ........................................................................................ 46
2.9.1 Debug Interrupt Enable Register (DIER) ...................................................................... 47
2.9.2 DSP Core Number Register (DNUM) .......................................................................... 48
2.9.3 Exception Clear Register (ECR) ................................................................................ 48
2.9.4 Exception Flag Register (EFR) ................................................................................. 49
2.9.5 GMPY Polynomial—A Side Register (GPLYA) ............................................................... 50
2.9.6 GMPY Polynomial—B Side Register (GPLYB) ............................................................... 50
2.9.7 Internal Exception Report Register (IERR) ................................................................... 51
2.9.8 SPLOOP Inner Loop Count Register (ILC) ................................................................... 52
2.9.9 Interrupt Task State Register (ITSR) ........................................................................... 52
2.9.10 NMI/Exception Task State Register (NTSR) ................................................................. 53
2.9.11 Restricted Entry Point Register (REP) ........................................................................ 53
2.9.12 SPLOOP Reload Inner Loop Count Register (RILC) ....................................................... 54
2.9.13 Saturation Status Register (SSR) ............................................................................. 54
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Copyright © 2010, Texas Instruments Incorporated
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2.9.14 Time Stamp Counter Registers (TSCL and TSCH) ......................................................... 55
2.9.15 Task State Register (TSR) ..................................................................................... 57
2.10 Control Register File Extensions for Floating-Point Operations ..................................................... 58
2.10.1 Floating-Point Adder Configuration Register (FADCR) ..................................................... 59
2.10.2 Floating-Point Auxiliary Configuration Register (FAUCR) .................................................. 61
2.10.3 Floating-Point Multiplier Configuration Register (FMCR) ................................................... 63
3 Instruction Set .................................................................................................................. 65
3.1 Instruction Operation and Execution Notations ........................................................................ 66
3.2 Instruction Syntax and Opcode Notations .............................................................................. 68
3.2.1 32-Bit Opcode Maps ............................................................................................. 69
3.2.2 16-Bit Opcode Maps ............................................................................................. 69
3.3 Overview of IEEE Standard Single- and Double-Precision Formats ............................................... 70
3.3.1 Single-Precision Formats ........................................................................................ 71
3.3.2 Double-Precision Formats ....................................................................................... 72
3.4 Delay Slots ................................................................................................................. 73
3.5 Parallel Operations ........................................................................................................ 74
3.5.1 Example Parallel Code .......................................................................................... 76
3.5.2 Branching Into the Middle of an Execute Packet ............................................................. 76
3.6 Conditional Operations ................................................................................................... 77
3.7 SPMASKed Operations ................................................................................................... 77
3.8 Resource Constraints ..................................................................................................... 78
3.8.1 Constraints on Instructions Using the Same Functional Unit ............................................... 78
3.8.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle ........................ 78
3.8.3 Constraints on Cross Paths (1X and 2X) ...................................................................... 78
3.8.4 Cross Path Stalls ................................................................................................. 79
3.8.5 Constraints on Loads and Stores .............................................................................. 80
3.8.6 Constraints on Long (40-Bit) Data .............................................................................. 80
3.8.7 Constraints on Register Reads ................................................................................. 81
3.8.8 Constraints on Register Writes ................................................................................. 81
3.8.9 Constraints on AMR Writes ..................................................................................... 82
3.8.10 Constraints on Multicycle NOPs ............................................................................... 82
3.8.11 Constraints on Unitless Instructions .......................................................................... 82
3.8.12 Constraints on Floating-Point Instructions ................................................................... 85
3.9 Addressing Modes ......................................................................................................... 87
3.9.1 Linear Addressing Mode ......................................................................................... 87
3.9.2 Circular Addressing Mode ....................................................................................... 88
3.9.3 Syntax for Load/Store Address Generation ................................................................... 90
3.10 Compact Instructions on the CPU ....................................................................................... 91
3.10.1 Compact Instruction Overview ................................................................................. 91
3.10.2 Header Word Format ........................................................................................... 92
3.10.3 Processing of Fetch Packets ................................................................................... 96
3.10.4 Execute Packet Restrictions ................................................................................... 96
3.10.5 Available Compact Instructions ................................................................................ 96
3.11 Instruction Compatibility .................................................................................................. 97
3.12 Instruction Descriptions ................................................................................................... 98
4 Pipeline .......................................................................................................................... 575
4.1 Pipeline Operation Overview ........................................................................................... 576
4.1.1 Fetch .............................................................................................................. 577
4.1.2 Decode ........................................................................................................... 578
4.1.3 Execute ........................................................................................................... 579
4.1.4 Pipeline Operation Summary .................................................................................. 580
4.2 Pipeline Execution of Instruction Types ............................................................................... 585
4.2.1 Single-Cycle Instructions ....................................................................................... 588
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Contents SPRUFE8A–May 2010
Copyright © 2010, Texas Instruments Incorporated
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4.2.2 Two-Cycle Instructions and .M Unit Nonmultiply Operations ............................................. 589
4.2.3 Store Instructions ............................................................................................... 590
4.2.4 Extended Multiply Instructions ................................................................................. 592
4.2.5 Load Instructions ................................................................................................ 593
4.2.6 Branch Instructions ............................................................................................. 594
4.2.7 Two-Cycle DP Instructions ..................................................................................... 596
4.2.8 Four-Cycle Instructions ......................................................................................... 597
4.2.9 INTDP Instruction ............................................................................................... 598
4.2.10 Double-Precision (DP) Compare Instructions .............................................................. 598
4.2.11 ADDDP/SUBDP Instructions ................................................................................. 599
4.2.12 MPYI Instruction ................................................................................................ 599
4.2.13 MPYID Instruction .............................................................................................. 600
4.2.14 MPYDP Instruction ............................................................................................. 600
4.2.15 MPYSPDP Instruction ......................................................................................... 601
4.2.16 MPYSP2DP Instruction ....................................................................................... 601
4.3 Functional Unit Constraints ............................................................................................. 602
4.3.1 .S-Unit Constraints .............................................................................................. 602
4.3.2 .M-Unit Constraints ............................................................................................. 606
4.3.3 L-Unit Constraints ............................................................................................... 614
4.3.4 D-Unit Instruction Constraints ................................................................................. 618
4.4 Performance Considerations ........................................................................................... 621
4.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet ................................... 621
4.4.2 Multicycle NOPs ................................................................................................. 623
4.4.3 Memory Considerations ........................................................................................ 624
5 Interrupts ........................................................................................................................ 627
5.1 Overview .................................................................................................................. 628
5.1.1 Types of Interrupts and Signals Used ........................................................................ 628
5.1.2 Interrupt Service Table (IST) .................................................................................. 630
5.1.3 Summary of Interrupt Control Registers ..................................................................... 634
5.2 Globally Enabling and Disabling Interrupts ........................................................................... 634
5.3 Individual Interrupt Control .............................................................................................. 637
5.3.1 Enabling and Disabling Interrupts ............................................................................. 637
5.3.2 Status of Interrupts .............................................................................................. 637
5.3.3 Setting and Clearing Interrupts ................................................................................ 638
5.3.4 Returning From Interrupt Servicing ........................................................................... 638
5.4 Interrupt Detection and Processing .................................................................................... 639
5.4.1 Setting the Nonreset Interrupt Flag ........................................................................... 639
5.4.2 Conditions for Processing a Nonreset Interrupt ............................................................. 640
5.4.3 Saving TSR Context in Nonreset Interrupt Processing .................................................... 642
5.4.4 Actions Taken During Nonreset Interrupt Processing ...................................................... 643
5.4.5 Conditions for Processing a Nonmaskable Interrupt ....................................................... 643
5.4.6 Saving of Context in Nonmaskable Interrupt Processing .................................................. 646
5.4.7 Actions Taken During Nonmaskable Interrupt Processing ................................................ 646
5.4.8 Setting the RESET Interrupt Flag ............................................................................. 646
5.4.9 Actions Taken During RESET Interrupt Processing ........................................................ 647
5.5 Performance Considerations ........................................................................................... 648
5.5.1 General Performance ........................................................................................... 648
5.5.2 Pipeline Interaction ............................................................................................. 648
5.6 Programming Considerations .......................................................................................... 648
5.6.1 Single Assignment Programming ............................................................................. 648
5.6.2 Nested Interrupts ................................................................................................ 649
5.6.3 Manual Interrupt Processing (polling) ........................................................................ 650
5.6.4 Traps .............................................................................................................. 651
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SPRUFE8A–May 2010 Contents
Copyright © 2010, Texas Instruments Incorporated
