LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b:IN STD_LOGIC;
CO,SO:OUt STD_LOGIC);
end ENTITY H_ADDER;
ARCHITECTURE FH1 OF H_ADDER IS
begin
SO<=NOT(A XOR (NOT B)); CO<=A AND B;
END ARCHITECTURE FH1;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY or2a IS
port(a,b:in std_logic;
c:out std_logic);
END ENTITY or2a;
ARCHITECTURE one of or2a IS
begin
c<=a OR b;
END one;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY f_adder IS
PORT (ain,bin,cin :IN STD_LOGIC;
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