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mnl_avalon_spec NIOS II 开发手册
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mnl_avalon_spec Nios ii 开发手册,不必多说,我想你懂的。
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Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-
tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Avalon Interface Specifications
MNL-AVABUSREF-1.1
Altera Corporation i
Table of Contents
1.1. Avalon Properties and Parameters ..................................................................................................1–4
1.2. Signal Types ........................................................................................................................................1–4
1.3. Interface Timing .................................................................................................................................1–5
1.4. Related Documents ............................................................................................................................1–5
2.1. Clock Input (Sink) ..............................................................................................................................2–1
2.1.1. Properties ...............................................................................................................................2–2
2.1.2. Signal Types ..........................................................................................................................2–2
2.1.3. associatedClock Interfaces ..................................................................................................2–2
2.2. Clock Output (Source) .......................................................................................................................2–2
2.2.1. Properties ...............................................................................................................................2–3
2.2.2. Signal Types ..........................................................................................................................2–3
3.1. Introduction .........................................................................................................................................3–1
3.2. Slaves ....................................................................................................................................................3–3
3.3. Slave Interface Properties ..................................................................................................................3–5
3.4. Slave Timing ........................................................................................................................................3–8
3.4.1. Synchronous Interface .........................................................................................................3–8
3.4.2. Performance ..........................................................................................................................3–8
3.4.3. Electrical Characteristics .....................................................................................................3–8
3.5. Slave Transfers ....................................................................................................................................3–8
3.5.1. Typical Slave Read and Write Transfers ...........................................................................3–8
3.5.2. Slave Read and Write Transfers with Fixed Wait-States ................................................3–9
3.5.3. Pipelined Transfers ............................................................................................................3–10
3.5.3.1. Slave Pipelined Read Transfer with Variable Latency ....................................... 3–11
3.5.3.2. Restrictions ................................................................................................................ 3–12
3.5.3.3. Slave Pipelined Read Transfer with Fixed Latency ............................................ 3–12
3.5.4. Burst Transfers ....................................................................................................................3–13
3.5.4.1. Slave Write Bursts .................................................................................................... 3–14
3.5.4.2. Slave Read Bursts ..................................................................................................... 3–15
3.5.4.3. Line–Wrapped Bursts .............................................................................................. 3–16
3.5.4.4. Flow Control ............................................................................................................. 3–17
3.6. Address Alignment ...........................................................................................................................3–17
3.7. Masters ...............................................................................................................................................3–19
3.8. Master Signal Types ..........................................................................................................................3–20
3.9. Master Interface Properties ..............................................................................................................3–23
3.10. Master Transfers ..............................................................................................................................3–24
3.10.1. Master Pipelined Read Transfer .....................................................................................3–25
3.10.2. Burst Transfers ..................................................................................................................3–27
3.10.2.1. Master Write Bursts ............................................................................................... 3–27
3.10.2.2. Master Read Bursts ................................................................................................ 3–28
4.1. Interrupt Sender ..................................................................................................................................4–1
4.1.1. Signal Types ..........................................................................................................................4–1
ii Altera Corporation
Avalon Interface Specifications
Table of Contents
4.1.2. Interrupt Sender Properties ................................................................................................4–2
4.2. Interrupt Receiver ...............................................................................................................................4–2
4.2.1. Interrupt Receiver Properties .............................................................................................4–3
4.2.2. Signal Types ..........................................................................................................................4–3
4.2.3. Interrupt Timing ...................................................................................................................4–3
5.1. Tristate Slave Signal Types ................................................................................................................5–2
5.1.1. address Behavior ..................................................................................................................5–3
5.1.2. outputenable and read Behavior ........................................................................................5–4
5.1.3. write_n and writebyteenable Behavior .............................................................................5–4
5.1.4. Interfacing to Synchronous Off-Chip Memory ................................................................5–5
5.2. Tristate Slave Properties ....................................................................................................................5–6
5.3. Slave Transfers ....................................................................................................................................5–6
5.3.1. Asynchronous Transfers .....................................................................................................5–6
5.3.1.1. Setup Time .................................................................................................................. 5–7
5.3.1.2. Hold Time ................................................................................................................... 5–8
5.3.1.3. Example Read and Write Using Setup, Hold and Wait Times ........................... 5–8
5.3.2. Synchronous Transfers ......................................................................................................5–10
5.3.3. Pipelined Slave Read Transfers ........................................................................................5–10
5.4. Master Transfers ................................................................................................................................5–12
6.1. Introduction .........................................................................................................................................6–1
6.1.1. Features ..................................................................................................................................6–2
6.1.2. Terms and Concepts ............................................................................................................6–2
6.2. Avalon-ST Interface Signals ..............................................................................................................6–3
6.2.1. Signal Polarity .......................................................................................................................6–4
6.2.2. Signal Sequencing and Timing ...........................................................................................6–5
6.2.2.1. Synchronous Interface ............................................................................................... 6–5
6.2.2.2. Clock Enables .............................................................................................................. 6–5
6.3. Avalon-ST Interface Properties .........................................................................................................6–5
6.4. Typical Data Transfers .......................................................................................................................6–6
6.4.1. Signal Details ........................................................................................................................6–6
6.4.2. Data Layout ...........................................................................................................................6–7
6.5. Data Transfer without Backpressure ................................................................................................6–8
6.6. Data Transfer with Backpressure .....................................................................................................6–9
6.7. Packet Data Transfers .......................................................................................................................6–10
6.7.1. Signal Details ......................................................................................................................6–11
6.7.2. Protocol Details ...................................................................................................................6–11
7.1. Properties .............................................................................................................................................7–2
7.2. Signals ...................................................................................................................................................7–2
Document Revision History ..................................................................................................................Info–1
How to Contact Altera ...........................................................................................................................Info–1
Typographic Conventions .....................................................................................................................Info–2
Altera Corporation 1–1
October 2008
1. Introduction
Avalon
®
interfaces simplify system design by allowing you to easily
connect components in an FPGA. The Avalon interface family defines
interfaces for use in both high-speed streaming and memory-mapped
applications. These standard interfaces are designed into the components
available in the system-on-a-programmable-chip (SOPC) environment
and the MegaWizard Plug-In Manager. You can also use these
standardized interfaces in your custom components.
This specification defines all of the Avalon interfaces. After reading it,
you should understand which interfaces are appropriate for your
components and which signal types are used for which desired
behaviors. There are six different interface types:
■ Avalon Memory Mapped Interface (Avalon-MM)—an address-based
read/write interface typical of master–slave connections
■ Avalon Streaming Interface (Avalon-ST)—an interface that supports
the unidirectional flow of data, including multiplexed streams,
packets, and DSP data
■ Avalon Memory Mapped Tristate Interface—an address-based
read/write interface to support off-chip peripherals. Multiple
peripherals can share data and address buses to reduce the pincount
of an FPGA and the number of traces on the PCB
■ Avalon Clock—an interface that drives or receives clock and reset
signals to synchronize interfaces and provide reset connectivity
■ Avalon Interrupt—an interface that allows components to signal
events to other components
■ Avalon Conduit—an interface that allows signals to be exported out
at the top level of an SOPC Builder system where they can be
connected to other modules of the design or FPGA pins
A single component can include any number of these interfaces and can
also include multiple instances of the same interface type. For example, in
Figure 1.1, the Ethernet Controller includes four different interface types:
Avalon-MM, Avalon-ST, clock, and conduit.
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