# pxlba generated file
# pxlBA.txt : Extract file used to extract properties for
# back annotation using packagerxl. Refer to Allegro extract
# documentation for more details on the syntax of this file
# and the Extract program.
# The lines starting with # are comments.
# The default version of this file extracts the minimum number
# of properties necessary to ba changes to packaging.
# To extract additional properties the user must remove the
# comment character '#' from the appropriate lines. Or
# add a line with the property name to the appropriate section.
# a2pxl looks for this file in the current working directory.
# If it is not found there, it looks for it
# in the hierarchy in the following location:
# <installation dir>/tools/pcb/text/views
# Connection view. File: pinView.dat
#
LOGICAL_PIN
# These properties must not be removed, moved or modified.
# vvvvvvvvvvvvvvvvvvv
NET_NAME
REFDES
PIN_NUMBER
FUNC_LOGICAL_PATH
COMP_DEVICE_TYPE
FUNC_SCH_SIZE
FUNC_HAS_FIXED_SIZE
FUNC_DES
# ^^^^^^^^^^^^^^^^^^^
# Any other PIN properties to be back annotated show up here.
PIN_NET_SHORT
PIN_NO_SWAP_PIN
PIN_NO_PIN_ESCAPE
PIN_PIN_ESCAPE
PIN_PIN_SIGNAL_MODEL
PIN_NO_DRC
PIN_NO_SHAPE_CONNECT
END
# Function properties view. File: funcView.dat
# In order to backannotate function properties you must
# include FUNC_LOGICAL_PATH.
#
FUNCTION
FUNC_LOGICAL_PATH
COMP_DEVICE_TYPE
REFDES
FUNC_PRIM_FILE
COMP_PARENT_PPT
COMP_PARENT_PPT_PART
COMP_PARENT_PART_TYPE
FUNC_SCH_SIZE
FUNC_HAS_FIXED_SIZE
FUNC_DES
FUNC_GROUP
FUNC_ROOM
FUNC_CDS_FSP_UID
FUNC_NO_SWAP_PIN
FUNC_HARD_LOCATION
FUNC_NO_SWAP_GATE_EXT
FUNC_CDS_FSP_MAPPED_CELL
FUNC_CDS_FSP_FPGA_SYMBOL
FUNC_CDS_FSP_TERM_TYPE
FUNC_CDS_FSP_TERM_NAME
FUNC_ROOM
FUNC_GROUP
FUNC_CDS_FSP_TERM_INDEX
FUNC_NO_SWAP_GATE
END
# Component properties view. File: compView.dat
# In order to backannotate component properties you must
# include REFDES
#
COMPONENT
REFDES
COMP_VOLTAGE
COMP_PLACE
COMP_CDS_FSP_LIB_PART_MODEL
COMP_CDS_FSP_INSTANCE_NAME
COMP_ROOM
COMP_GROUP
COMP_SIGNAL_MODEL
COMP_CDS_FSP_INSTANCE_ID
COMP_NO_XNET_CONNECTION
COMP_CDS_FSP_IS_FPGA
# The following two properties are needed to feedback ppt
# part selections done in Allegro.
# You may comment them out if you do not use this functionality.
COMP_PARENT_PPT
COMP_PARENT_PPT_PART
COMP_REUSE_ID
COMP_REUSE_NAME
COMP_REUSE_INSTANCE
END
#
# Signal properties view. File: netView.dat
# In order to backannotate signal properties you must
# include NET_NAME
#
NET
NET_NAME
NET_LOGICAL_PATH
NET_CDS_FSP_UID
NET_SHIELD_NET
NET_RELATIVE_PROPAGATION_DELAY
NET_NO_PIN_ESCAPE
NET_NET_SHORT
NET_VOLTAGE_LAYER
NET_VOLTAGE
NET_RATSNEST_SCHEDULE
NET_CLOCK_NET
NET_NET_PHYSICAL_TYPE
NET_MAX_FINAL_SETTLE
NET_NO_TEST
NET_MAX_EXPOSED_LENGTH
NET_ELECTRICAL_CONSTRAINT_SET
NET_CDS_FSP_BUS_INDEX
NET_STUB_LENGTH
NET_SHIELD_TYPE
NET_NO_RAT
NET_PROPAGATION_DELAY
NET_NO_RIPUP
NET_MIN_HOLD
NET_DIFFERENTIAL_PAIR
NET_MIN_SETUP
NET_MIN_NECK_WIDTH
NET_BUS_NAME
NET_MIN_NOISE_MARGIN
NET_MATCHED_DELAY
NET_ECL
NET_DIFFP_LENGTH_TOL
NET_DIFFP_2ND_LENGTH
NET_NET_GROUP_GRP_NAME
NET_SUBNET_NAME
NET_MIN_BOND_LENGTH
NET_MAX_OVERSHOOT
NET_TS_ALLOWED
NET_MAX_VIA_COUNT
NET_EMC_CRITICAL_NET
NET_CDS_FSP_NET
NET_PROBE_NUMBER
NET_NO_ROUTE
NET_MIN_LINE_WIDTH
NET_ECL_TEMP
NET_NO_GLOSS
NET_ROUTE_PRIORITY
NET_NET_SPACING_TYPE
NET_IMPEDANCE_RULE
END
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i.mx6UL原理图和PCB allegro格式
共61个文件
log:21个
dat:8个
txt:4个
需积分: 15 17 下载量 57 浏览量
2018-05-22
08:57:13
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i.mx6UL原理图和PCB allegro格式,本人自己学习高速PCB的第一块板子,DDR走线没考虑过孔长度,应该同组同层的
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收起资源包目录
i_MX6UL_core.rar (61个子文件)
i_MX6UL_core
pstxnet.dat 241KB
signoise.run
cases.cfg 80B
case1
sigsimcntl.dat 85B
sigsimres.dat 579B
netlist.log 20KB
cmpshape.log 835B
nccustomization.log 698B
stepFacetFiles4Map
DRC
I_MX6UL_CORE.DRC 25KB
quickplace.log 661B
router_long.log 4KB
embedded_layer_setup.log 89B
signoise.log 250B
i_MX6UL_core.xml 71B
refresh.log 3KB
mosaic.log 44B
ENET1_CRS_DV.top 26KB
Gerber
sigxp.dml 4KB
allegro_S06616.6-2015_AllegroMiniDump.dmp 61KB
i_MX6UL_core.brd 3.88MB
shape_islands.rpt 786B
i_MX6UL_core_gre.log 913B
license_use.log 260B
csetApply.log 0B
enternet.mdd 264KB
pxlBA.txt 4KB
pstxprt.dat 175KB
specctra.did 148KB
i_MX6UL_core.opj 10KB
netrev.lst 3KB
i_MX6UL_core_gre_bak.log 966B
sigxp.run
cases.cfg 80B
case0
waveforms
batch_drc.log 1KB
.rtcomp 68B
emmc4.5.mdd 290KB
sigxp.jrl 2KB
I_MX6UL_CORE_0.DBK 832KB
i_MX6UL_core_sch.xml 87KB
master.tag 18B
gloss.log 37KB
vdd_snvs_3v3.mdd 189KB
Create_Netlist
pstxnet.dat 242KB
netlist.log 19KB
pxlBA.txt 4KB
pstxprt.dat 176KB
netrev.lst 3KB
eco.txt 2KB
pstchip.dat 90KB
i_MX6UL_core.SAV 2.73MB
eco.txt 1KB
devices.dml 43B
split_plane.log 742B
specctra.log 27KB
allegro.jrl 97KB
interconn.iml 74KB
router.log 1KB
monitor.sts 3KB
i_MX6UL_core.dsn 832KB
mosaic_bak.log 44B
convert_corner.log 1KB
pstchip.dat 90KB
vcc_3v3.mdd 187KB
共 61 条
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