JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-3F
JULY 2012
JEDEC
STANDARD
DDR3 SDRAM Standard
(Revision of JESD79-3E, July 2010)
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JEDEC Standard No. 79-3F
Contents
i
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table .....................................................................................................33
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
4.9.1 Self-Refresh Temperature Range - SRT...................................................................46
4.10.1 MPR Functional Description ..................................................................................49
4.10.2 MPR Register Address Definition ..........................................................................50
4.10.3 Relevant Timing Parameters...................................................................................50
4.10.4 Protocol Example....................................................................................................50
4.12 PRECHARGE Command ..............................................................................................55
4.13.1 READ Burst Operation...........................................................................................56
4.13.3 Burst Read Operation followed by a Precharge......................................................66
4.14.1 DDR3 Burst Operation ...........................................................................................68
4.14.2 WRITE Timing Violations .....................................................................................68
4.14.3 Write Data Mask .....................................................................................................69
4.14.4 tWPRE Calculation.................................................................................................70
4.14.5 tWPST Calculation .................................................................................................70
4.17.1 Power-Down Entry and Exit...................................................................................81
4.17.2 Power-Down clarifications - Case 1 .......................................................................86
4.17.3 Power-Down clarifications - Case 2 .......................................................................87
5 On-Die Termination (ODT).....................................................................................................89
5.1 ODT Mode Register and ODT Truth Table.....................................................................89
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