www.chalayout.com – nfmao
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常用时序分析 SDC 命令参考
1. Define design environment
1.1. Set_operating_conditions
1.2. Set_wire_load_model
1.3. Set_driving_cell
1.4. Set_load
1.5. Set_fanout_load
1.6. Set_min_library
2. Set design constraints
2.1. Design rule constraints
2.1.1. Set_max_transition
2.1.2. Set_max_fanout
2.1.3. Set_max_capacitance
2.2. Design optimization constraints
2.2.1. Create_clock
2.2.2. create_generated_clock
2.2.3. Set_clock_latency
2.2.4. Set_propagated_clock
2.2.5. Set_clock_uncertainty
2.2.6. Set_input_delay
2.2.7. Set_output_delay
2.2.8. Set_max_area
3. Other commands
3.1. set_clock_groups
3.2. set_false_path
3.3. set_case_analysis
3.4. set_max_delay
1. Do not exist in timing fix sdc file:
1.1. Set_max_area
1.2. set_operation_conditions
1.3. set_wire_load_model
1.4. set_ideal_*
2. Must be placed in timing fix sdc file:
2.1. Set_clock_uncertainty,
2.2. set_max_transition
2.3. set_propagated_clock
