没有合适的资源?快使用搜索试试~ 我知道了~
温馨提示
试读
281页
Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and parallelize, at the same time, the communication among the modules of the system. The switches are the basic building blocks of such networks, and their design critically affects the performance of the whole system. The way data traverse each switch is governed by the operation of the arbiter and the crossbar鈥檚 multiplexers that need to be efficiently mapped on the FPGA fabric.
资源推荐
资源详情
资源评论
Editors
Peter Athanas
Bradley Department of Electrical
and Computer Engineering
Virginia Tech
BLACKSBURG, Virgin Islands
USA
Nicolas Sklavos
KNOSSOSnet Research Group
Informatics & MM Department
Technological Educational Institute
of Patras, Greece
Dionisios Pnevmatikatos
Technical University of Crete
Crete, Greece
ISBN 978-1-4614-1361-5 ISBN 978-1-4614-1362-2 (eBook)
DOI 10.1007/978-1-4614-1362-2
Springer New York Heidelberg Dordrecht London
Library of Congress Control Number: 2012951421
© Springer Science+Business Media, LLC 2013
This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of
the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,
broadcasting, reproduction on microfilms or in any other physical way, and transmission or information
storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology
now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection
with reviews or scholarly analysis or material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of
this publication or parts thereof is permitted only under the provisions of the Copyright Law of the
Publisher’s location, in its current version, and permission for use must always be obtained from Springer.
Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations
are liable to prosecution under the respective Copyright Law.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication
does not imply, even in the absence of a specific statement, that such names are exempt from the relevant
protective laws and regulations and therefore free for general use.
While the advice and information in this book are believed to be true and accurate at the date of
publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for
any errors or omissions that may be made. The publisher makes no warranty, express or implied, with
respect to the material contained herein.
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)
www.allitebooks.com
Preface
This book presents methodologies for embedded systems design, using field
programmable gate array (FPGA) devices, for the most modern applications. This
manuscript covers state-of-the-art research from academia and industry on a wide
range of topics, including applications, advanced electronic design automation
(EDA), novel system architectures, embedded processors, arithmetic, and dynamic
reconfiguration.
The book organization is based on 11 chapters, which cover different issues and
deal with alternative scientific issues and industrial areas. The description of each
chapter in a more analyticalmannerisasfollows:
Chapter 1 presents a lightweight extension to statically scheduled microarchitec-
tures for speculative execution: PreCoRe. Its judicious use of an efficient dynamic
token model allows to predict, commit, and replay speculation events. Even if the
speculation fails continuously, no additional execution cycles are required over the
original static schedule. PreCoRe relies on MARC II, a high-performance multi-port
memory system based on application-specific coherency mechanisms for distributed
caches, and on RAP, a technique to efficiently resolve memory dependencies for
speculatively reordered accesses.
The field which Chap. 2 deals with is decimal arithmetic. The importance of
decimal for computer arithmetic has been further and definitely recognized by its
inclusion in the recent revision of the IEEE-754 2008 standard for floating-point
arithmetic. The authors propose a new iterative decimal divider. The divider uses
the Newton–Raphson iterative method, with an initial piecewise approximation
calculated with a minimax polynomial, and is able to take full advantage of
the embedded binary multipliers available in today’s FPGA technologies. The
comparisons of the implementation results indicate that the proposed divider is very
competitive in terms of area and latency and better in terms of throughput when
compared to decimal dividers based on digit-recurrence algorithms.
Chapter 3 presents the design and mapping of a low-cost logic-level aging
sensor for FPGA-based designs. The mapping of this sensor is designed to provide
controlled sensitivity, ranging from a warning sensor to a late transition detector. It
provides also a selection scheme to determine the most aging-critical paths at which
v
www.allitebooks.com
剩余280页未读,继续阅读
资源评论
yadunhaha
- 粉丝: 5
- 资源: 25
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功