基于fpga的ad采样

基于fpga与ad之间的高速采样， LCD_EN : out std_logic; --液晶时钟信号 ad_in:in std_logic_vector(7 downto 0); LCD_Data : out std_logic_vector(7 downto 0)); --液晶数据信号 end LCD1602; architecture Behavioral of LCD1602 is type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data); signal Current_State:state; signal Clk_Out : std_logic; signal LCD_Clk : std_logic; signal temp,wan,qian,bai,shi,ge:integer range 0 to 5:=0; type ram1 is array(0 to 15) of std_logic_vector(7 downto 0); type ram2 is array(0 to 15) of std_logic_vector(7 downto 0); constant cgram1 : ram1 :=(x"54",x"48",x"45",x"20",x"56",x"20",x"49",x"53",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20"); constant cgram2 : ram2 :=(x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37",x"38",x"39",x"20",x"20",x"20",x"20",x"20",x"20");