EDA数字钟设计

24进制计数器：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter24 is
    Port ( clr : in std_logic;
           clk : in std_logic;
           en : in std_logic;
           lsq : inout std_logic_vector(3 downto 0);
           msq : inout std_logic_vector(3 downto 0));
end counter24;

architecture Behavioral_counter of counter24 is
-- signal 
begin
    process(clr, clk, en)
    begin
        if (en = '1' or clr = '0') then
            lsq <= "0011";
  msq <= "0010";
        elsif (rising_edge(clk)) then
       if (lsq = "0011" and msq= "0010") then
      lsq <= "0000";
 msq <= "0000";
            elsif (lsq = "1001") then
     msq <= msq + '1';
lsq <= "0000";
  else